M95040-MN6 Ver la hoja de datos (PDF) - STMicroelectronics

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M95040-MN6

4/2/1 Kbit Serial SPI Bus EEPROM With High Speed Clock

STMicroelectronics 

M95040, M95020, M95010

Status Register

Figure 8 shows the position of the Status Register

in the control logic of the device. This register con-

tains a number of control bits and status bits, as

shown in Table 2.

Bits b7, b6, b5 and b4 are always read as 1.

WIP bit. The Write In Progress bit is a volatile

read-only bit that is automatically set and reset by

the internal logic of the device. When set to a 1, it

indicates that the memory is busy with a Write cy-

cle.

WEL bit. The Write Enable Latch bit is a volatile

read-only bit that is set and reset by specific in-

structions. When reset to 0, no WRITE or WRSR

instructions are accepted by the device.

BP1, BP0 bits. The Block Protect bits are non-

volatile read-write bits. These bits define the area

of memory that is protected against the execution

of Write cycles, as summarized in Table 3.

Table 2. Status Register Format

b7

b0

1

1

1

1 BP1 BP0 WEL WIP

Block Protect Bits

Write Enable Latch Bit

Write In Progress Bit

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