PCD5042 Ver la hoja de datos (PDF) - Philips Electronics
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PCD5042 Datasheet PDF : 28 Pages
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Philips Semiconductors
DECT burst mode controller
Objective specification
PCD5042
SYMBOL
PIN
TYPE(2)
QFP64 LQFP80(1)
DESCRIPTION
R_ENABLE
54
R_POWER_DWN
55
COMP_NE
−
SLICE_CTR
56
COMP_OUT
−
VDD3
57
VSS5
58
COMP_INM
−
VREF
59
COMP_INP
−
VDD(RAM)
60
SYNCPORT
61
RESET
62
MEM_SEL
63
EN_WATCHDOG
64
64
O receiver enable (active LOW)
65
O receiver power-down
66
I
digital input comparator not_enable (active LOW)
67
O slice time constant control
68
O digital comparator output
69
P positive supply 3
70
P negative supply 5
71
I
analog comparator input negative
72
I
reference input for the A/D converter
73
I
analog input positive
74
P power supply for data RAM
76
I/O in the base station the signal is the SYNCPORT
77
I
BMC master reset signal
78
I
selects PCC program memory at microcontroller interface
79
I
enable watchdog input; when HIGH, the watchdog timer of
the BMC is enabled
Notes
1. Un-referenced pins for the LQFP80 package are not connected. FS3, FS4 and the comparator signals are only
available in the LQFP80 package.
2. All signals which are input or I/O, and which can be floating, need to be pulled up to VDD or down to VSS in order to
protect the device against cross-currents. Exceptions are VREF and RSSI_AN, which do not have to be protected.
1996 Oct 31
6
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