IDT54FCT88915TT100L Ver la hoja de datos (PDF) - Integrated Device Technology
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IDT54FCT88915TT100L Datasheet PDF : 11 Pages
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IDT54/74FCT88915TT 55/70/100/133
LOW SKEW PLL-BASED CMOS CLOCK DRIVER
PIN CONFIGURATIONS
MILITARY AND COMMERCIAL TEMPERATURE RANGES
4 3 2 1 28 27 26
FEEDBK 5
25 Q/2
REF_SEL 6
24 GND
SYNC(0) 7
VCC(AN) 8
LF 9
J28-1,
L28-1
23 Q3
22 VCC
21 Q2
GND(AN) 10
20 GND
SYNC(1) 11
19 LOCK
12 13 14 15 16 17 18
PLCC/LCC
TOP VIEW
3072 drw 02
GND
Q5
VCC
OE/RST
FEEDBACK
REF_SEL
SYNC(0)
VCC(AN)
LF
GND(AN)
SYNC(1)
FREQ_SEL
GND
Q0
1
28
2
27
3
26
4
25
5
24
6
23
7 SO28-7 22
8
21
9
20
10
19
11
18
12
17
13
16
14
15
SSOP
TOP VIEW
Q4
VCC
2Q
Q/2
GND
Q3
VCC
Q2
GND
LOCK
PLL_EN
GND
Q1
VCC
3072 drw 03
PIN DESCRIPTION
Pin Name
I/O
SYNC(0)
I
SYNC(1)
I
REF_SEL
I
FREQ_SEL
I
FEEDBACK
I
LF
I
Q0-Q4
O
Q5
O
2Q
O
Q/2
O
LOCK
O
OE/RST
I
PLL_EN
I
Description
Reference clock input.
Reference clock input.
Chooses reference between SYNC (0) & SYNC (1). (Refer to functional block diagram).
Selects between ÷1 and ÷2 frequency options. (Refer to functional block diagram).
Feedback input to phase detector.
Input for external loop filter connection.
Clock output.
Inverted clock output.
Clock output (2 x Q frequency).
Clock output (Q frequency ÷ 2).
Indicates phase lock has been achieved (HIGH when locked).
Asynchronous reset (active LOW) and output enable (active HIGH). When HIGH, outputs are
enabled. When LOW, outputs are in HIGH impedance.
Disables phase-lock for low frequency testing. (Refer to functional block diagram).
3072 tbl 01
9.7
2
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