GS880Z18BGT-150I(2004) Ver la hoja de datos (PDF) - Giga Semiconductor

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GS880Z18BGT-150I
(Rev.:2004)

9Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

GS880Z18/36BT-333/300/250/200/150

Flow Through Mode Data I/O State Diagram

BW

R

High Z

(Data In)

D

WR

High Z

B

D

RB

Data Out

W (Q Valid)

D

Key

Input Command Code

ƒ Transition

Current State (n)

Next State (n+1)

n

n+1

Clock (CK)

Notes

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B and D represent input command

codes as indicated in the Truth Tables.

n+2

n+3

Command

ƒ

ƒ

ƒ

ƒ

Current State

Next State

Current State and Next State Definition for: Pipeline and Flow Through Read Write Control State Diagram

Rev: 1.02 10/2004

10/24

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2001, GSI Technology

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