74HC20 Ver la hoja de datos (PDF) - NXP Semiconductors.
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74HC20 Datasheet PDF : 16 Pages
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NXP Semiconductors
74HC20; 74HCT20
Dual 4-input NAND gate
5.2 Pin description
Table 2. Pin description
Symbol
1A, 1B, 1C, 1D
n.c.
1Y
GND
2Y
2A, 2B, 2C, 2D
VCC
Pin
1, 2, 4, 5
3, 11
6
7
8
9, 10, 12, 13
14
6. Functional description
Description
data input
not connected
data output
ground (0 V)
data output
data input
supply voltage
Table 3. Function table[1]
Input
nA
nB
nC
nD
L
X
X
X
X
L
X
X
X
X
L
X
X
X
X
L
H
H
H
H
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care.
7. Limiting values
Output
nY
H
H
H
H
L
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
Parameter
Conditions
Min Max Unit
VCC
IIK
IOK
IO
ICC
IGND
Tstg
Ptot
supply voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
DIP14 package
VI < 0.5 V or VI > VCC + 0.5 V
VO < 0.5 V or VO > VCC + 0.5 V
0.5 V < VO < VCC + 0.5 V
0.5
[1] -
[1] -
-
-
50
65
[2]
-
+7
V
20 mA
20 mA
25 mA
50
mA
-
mA
+150 C
750 mW
SO14, and (T)SSOP14
packages
-
500 mW
[1] The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
[2] For DIP14 package: Ptot derates linearly with 12 mW/K above 70 C.
For SO14 package: Ptot derates linearly with 8 mW/K above 70 C.
For (T)SSOP14 packages: Ptot derates linearly with 5.5 mW/K above 60 C.
74HC_HCT20
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 3 — 3 September 2012
© NXP B.V. 2012. All rights reserved.
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