CMX264D5 Ver la hoja de datos (PDF) - CML Microcircuits

Número de pieza

componentes Descripción

Lista de partido

CMX264D5

Frequency Domain Split Band Scrambler

CML Microcircuits 

Frequency Domain Split Band Scrambler

CMX264

9. Measured at the output of the host transmit radio filter, such as shown in Figure 8.

10. The distortion figure of the expected output tone, whether that wanted tone is frequency

shifted or not. This parameter is defined as the rms value of the spurious tones specified in

Note 8 plus the noise within the measurement bandwidth, divided by the rms value of the total

signal, i.e. the wanted signal plus noise plus spurious tones.

11. Specified over the complete scrambling/descrambling process i.e. scrambling by the Tx

channel of the transmitting device, typical radio channel filtering such as shown in Figure 8

and descrambling by the Rx channel of the receiving device. The typical Rx channel

passband gain of the CMX264 receive section only is -1.0dB.

12. Not applicable in the region of the split point.

The response may exceed these limits within ±0.3 octaves of the frequencies 1950Hz,

1420Hz, 1180Hz and 980Hz (for split points 1 to 4, respectively).

Also, it may be outside ±3dB within ±0.15 octaves of the frequencies 1900Hz,

1450Hz, 1210Hz and 1000Hz (for split points 1 to 4, respectively).

In the recovered audio, some of the energy at the split point will have been transmitted in the

lowerband and some will have been transmitted in the upperband. When the Rx device

reconstitutes the signal, frequencies in the vicinity of the split point will consist of signals

summed together which have a random phase in relation to each other. The relative phase will

change over time so that the signals will vary between reinforcing each other or cancelling

each other, thus taking the response outside the given limits.

13. See Figures 9a and 9b for typical responses of the pre/de-emphasis circuits.

14. The internal state of the device is controlled by the data D0-D10 input at the serial interface.

Data should not be loaded until 3ms after initial power up to allow the reset circuit to complete

its operation and exit the RESET state..

15. No filtering is performed in clear mode, however there is a possibility of aliasing at 63.337kHz

(see Section 1.6.2.1).

© 1999 Consumer Microcircuits Limited

17

D/CMX264/1

Share Link: