HIP6019B Ver la hoja de datos (PDF) - Renesas Electronics
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HIP6019B Datasheet PDF : 15 Pages
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HIP6019B
VIN at the PHASE node. The PWM wave is smoothed by
the output filter (LO and CO).
VOSC
OSC
PWM
COMP
-
+
DRIVER
DRIVER
ZFB
VE/A
-
ZIN
ERROR +
AMP
REFERENCE
VIN
LO
VOUT
PHASE
CO
ESR
(PARASITIC)
DETAILED FEEDBACK COMPENSATION
C2
C1 R2
ZFB
VOUT
ZIN
C3 R3
R1
COMP
-
+
FB
HIP6019B
REFERENCE
FIGURE 11. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN
The modulator transfer function is the small-signal transfer
function of VOUT/VE/A. This function is dominated by a DC
gain and the output filter, with a double pole break frequency
at FLC and a zero at FESR. The DC gain of the modulator is
simply the input voltage, VIN, divided by the peak-to-peak
oscillator voltage, VOSC.
Modulator Break Frequency Equations
FLC=
-------------------1--------------------
2 LO CO
FESR=
--------------------1---------------------
2 ESR CO
The compensation network consists of the error amplifier
internal to the HIP6019B and the impedance networks ZIN
and ZFB. The goal of the compensation network is to
provide a closed loop transfer function with an acceptable
0dB crossing frequency (f0dB) and adequate phase margin.
Phase margin is the difference between the closed loop
phase at f0dB and 180degrees The equations below relate
the compensation network’s poles, zeros and gain to the
components (R1 , R2, R3 , C1 , C2, and C3) in Figure 11.
Use these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero below filter’s Double Pole (~75% FLC).
FN4587 Rev 1.00
April 13, 2005
3. Place 2ND Zero at filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at half the switching frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - repeat if necessary.
Compensation Break Frequency Equations
FZ1
=
-----------------1------------------
2 R2 C1
FP1
=
---------------------------1---------------------------
2
R2
C-C----11-----+-----CC-----22--
FZ2 = 2----------------R-----1-----+-1----R-----3------------C-----3-
FP2
=
-----------------1------------------
2 R3 C3
Figure 12 shows an asymptotic plot of the DC-DC
converter’s gain vs frequency. The actual modulator gain
has a peak due to the high Q factor of the output filter at FLC,
which is not shown in Figure 12. Using the above guidelines
should yield a compensation gain similar to the curve
plotted. The open loop error amplifier gain bounds the
compensation gain. Check the compensation gain at FP2
with the capabilities of the error amplifier. The closed loop
gain is constructed on the log-log graph of Figure 12 by
adding the modulator gain (in dB) to the compensation gain
(in dB). This is equivalent to multiplying the modulator
transfer function to the compensation transfer function and
plotting the gain.
100
FZ1 FZ2 FP1 FP2
80
60
OPEN LOOP
ERROR AMP GAIN
40
20LOG
20 (R2/R1)
0
MODULATOR
-20
GAIN
20LOG
(VIN/VOSC)
COMPENSATION
GAIN
-40
-60
FLC
FESR
CLOSED LOOP
GAIN
10
100
1K
10K 100K 1M 10M
FREQUENCY (Hz)
FIGURE 12. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth loop. A
stable control loop has a 0dB gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
Page 11 of 15
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