MD56V62160E-XXTA Ver la hoja de datos (PDF) - LAPIS Semiconductor Co., Ltd.

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MD56V62160E-XXTA

4-Bank x 1,048,576-Word x 16-Bit SYNCHRONOUS DYNAMIC RAM

LAPIS Semiconductor Co., Ltd. 

FEDD56V62160E-07

MD56V62160E

PIN DESCRIPTION

CLK

CS

CKE

Address

Fetches all inputs at the “H” edge.

Disables or enables device operation by asserting or deactivating all inputs except CLK, CKE,

UDQM and LDQM.

Masks system clock to deactivate the subsequent CLK operation.

If CKE is deactivated, system clock will be masked so that the subsequent CLK operation is

deactivated. CKE should be asserted at least one cycle prior to a new command.

Row & column multiplexed.

Row address

: RA0 – RA11

Column Address : CA0 – CA7

A13, A12 Slects bank to be activated during row address latch time and selects bank for precharge and

(BA0, BA1) read/write during column address latch time.

RAS

CAS

WE

UDQM,

LDQM

DQi

Functionality depends on the combination. For details, see the function truth table.

Masks the read data of two clocks later when UDQM and LDQM are set “H” at the “H” edge of the

clock signal. Masks the write data of the same clock when UDQM and LDQM are set “H” at the “H”

edge of the clock signal. UDQM controls upper byte and LDQM controls lower byte.

Data inputs/outputs are multiplexed on the same pin.

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