CY7C1041CV33-20VI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1041CV33-20VI Datasheet PDF : 12 Pages
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CY7C1041CV33
AC Switching Characteristics[5] Over the Operating Range
-8
-10
-12
-15
-20
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
Read Cycle
tpower[6]
VCC(typical) to the first access 1
tRC
Read Cycle Time
8
tAA
Address to Data Valid
tOHA
Data Hold from Address Change 3
tACE
CE LOW to Data Valid
tDOE
OE LOW to Data Valid
tLZOE
OE LOW to Low-Z
0
tHZOE
OE HIGH to High-Z[7, 8]
tLZCE
CE LOW to Low-Z[8]
3
tHZCE
CE HIGH to High-Z[7, 8]
tPU
CE LOW to Power-Up
0
tPD
CE HIGH to Power-Down
tDBE
Byte Enable to Data Valid
tLZBE
Byte Enable to Low-Z
0
tHZBE
Byte Disable to High-Z
Write Cycle[9, 10]
1
1
1
1
µs
10
12
15
20
ns
8
10
12
15
20 ns
3
3
3
3
ns
8
10
12
15
20 ns
4
5
6
7
8 ns
0
0
0
0
ns
4
5
6
7
8 ns
3
3
3
3
ns
4
5
6
7
8 ns
0
0
0
0
ns
8
10
12
15
20 ns
4
5
6
7
8 ns
0
0
0
0
ns
6
6
6
7
8 ns
tWC
Write Cycle Time
tSCE
CE LOW to Write End
tAW
Address Set-Up to Write End
tHA
Address Hold from Write End
tSA
Address Set-Up to Write Start
tPWE
WE Pulse Width
tSD
Data Set-Up to Write End
tHD
tLZWE
tHZWE
Data Hold from Write End
WE HIGH to Low-Z[8]
WE LOW to High-Z[7, 8]
tBW
Byte Enable to End of Write
Shaded areas contain advance information.
8
10
12
15
20
ns
6
7
8
10
10
ns
6
7
8
10
10
ns
0
0
0
0
0
ns
0
0
0
0
0
ns
6
7
8
10
10
ns
4
5
6
7
8
ns
0
0
0
0
0
ns
3
3
3
3
3
ns
4
5
6
7
8 ns
6
7
8
10
10
ns
Notes:
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
6. tPOWER gives the minimum amount of time that the power supply should be at typical VCC values until the first memory access can be performed.
7. tHZOE, tHZCE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.
8. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device.
9. The internal Write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a Write, and the transition of
either of these signals can terminate the Write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the
Write.
10. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document #: 38-05134 Rev. *E
Page 5 of 12
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