CY7C1041CV33-10BAXI(2008) Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY7C1041CV33-10BAXI Datasheet PDF : 14 Pages
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CY7C1041CV33
Switching Characteristics
Over the Operating Range [4]
Parameter
Description
Read Cycle
tpower[5]
tRC
tAA
tOHA
tACE
tDOE
tLZOE
tHZOE
tLZCE
tHZCE
tPU
tPD
tDBE
VCC(Typical) to the First Access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid Comm’l/Ind’l/Auto-A
OE LOW to Low Z[6]
OE HIGH to High Z[6, 7]
CE LOW to Low Z[6]
CE HIGH to High Z[6, 7]
Auto-E
CE LOW to Power Up
CE HIGH to Power Down
Byte Enable to Data Valid Comm’l/Ind’l/Auto-A
Auto-E
tLZBE
Byte Enable to Low Z
tHZBE
Byte Disable to High Z
Write Cycle[8, 9]
tWC
tSCE
tAW
tHA
tSA
tPWE
tSD
tHD
tLZWE
tHZWE
tBW
Write Cycle Time
CE LOW to Write End
Address Setup to Write End
Address Hold from Write End
Address Setup to Write Start
WE Pulse Width
Data Setup to Write End
Data Hold from Write End
WE HIGH to Low Z[6]
WE LOW to High Z[6, 7]
Byte Enable to End of Write
-10
Min Max
100
10
10
3
10
5
0
5
3
5
0
10
5
0
6
10
7
7
0
0
7
5
0
3
5
7
-12
Min Max
100
12
12
3
12
6
7
0
6
3
6
0
12
6
7
0
6
12
8
8
0
0
8
6
0
3
6
8
-15
Min Max
100
15
15
3
15
7
0
7
3
7
0
15
7
0
7
15
10
10
0
0
10
7
0
3
7
10
-20
Min Max
100
20
20
3
20
8
8
0
8
3
8
0
20
8
8
0
8
20
10
10
0
0
10
8
0
3
8
10
Unit
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, and input pulse levels of 0 to 3.0V.
5. tPOWER gives the minimum amount of time that the power supply is at typical VCC values until the first memory access is performed.
6. At any temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any device.
7. tHZOE, tHZCE, tHZBE, and tHZWE are specified with a load capacitance of 5 pF as in part (d) of AC Test Loads and Waveforms on page 5. Transition is measured ±500
mV from steady state voltage.
8. The internal write time of the memory is defined by the overlap of CE LOW, WE LOW, and BHE/BLE LOW. CE, WE, and BHE/BLE must be LOW to initiate a write.
The transition of these signals terminate the write. The input data setup and hold timing is referenced to the leading edge of the signal that terminates the write.
9. The minimum Write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of tHZWE and tSD.
Document Number: 38-05134 Rev. *I
Page 6 of 14
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