HD74AC166AFPEL Ver la hoja de datos (PDF) - Renesas Electronics

Número de pieza

componentes Descripción

Lista de partido

HD74AC166AFPEL

8-bit Shift Register

Renesas Electronics 

HD74AC166/HD74ACT166

Logic Symbol

15 2 3 4 5 10 11 12 14

PE P0 P1 P2 P3 P4 P5 P6 P7

1

DS

7

6

1

2

CP

MR

Q7

9

13

VCC=Pin16

GND=Pin8

Pin Names

CP1, CP2

DS

PE

P0 to P7

MR

Q7

Clock Pulse Inputs (Active Rising Edge)

Serial Data Input

Parallel Enable Input (Active Low)

Parallel Data Inputs

Asynchronous Master Reset Input (Active Low)

Last Stage Output

Functional Description

Operation is synchronous (except for Master Reset) and state changes are initiated by the rising edge of either clock

input if the other clock input is Low. When one of the clock inputs is used as an active High clock inhibt, it should

attain the High state while the other clock is still in the High state following the previous operation. When the Parallel

Enable (PE) input is Low, data is loaded into the register from the Parallel Data (P0 to P7) inputs on the next rising edge

of the clock. When PE is High, information is shifted from the Serial Data (DS) input to Q0 and all data in the register is

shifted one bit position (i.e., Q0 → Q1, Q1 → Q2, etc.) on the rising edge of the clock.

Truth Table

Inputs

MR

PE

L

X

CP2

X

CP1

X

H

X

L

L

H

L

L

H

H

L

H

H

L

H

X

H

H : High Voltage Level

L : Low Voltage Level

X : Immaterial

: Low-to-High Clock Transition

DS

X

X

X

H

L

X

Parallel

P0 to P7

X

L

X

QA0

a ··· h

a

X

H

X

L

X

QA0

Internal Outputs

Q0

Q6

L

QB0

b

QAn

QAn

QB0

Output

Q7

L

QH0

h

QGn

QGn

QH0

Rev.2.00, Jul.16.2004, page 2 of 8

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