HSP50214B Ver la hoja de datos (PDF) - Renesas Electronics
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HSP50214B Datasheet PDF : 62 Pages
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HSP50214B
NOTE: COF loading and timing is relative to CLKIN while SOF
loading and timing is relative to PROCCLK.
NOTE: TD can be 0, and the fastest rate is with 8-bit word width.
The assertion of the COFSYNC (or SOFSYNC) starts a count
down from the programmed word width. On following CLKs,
data is shifted into the register until the specified number of
bits have been input. At this point the contents of the register
are transferred from the Shift Register to the respective 32-bit
Holding Register. The Shift Register can accept new data on
the following CLK. If the serial input word is defined to be less
than 32-bits, it will be transferred to the MSBs of the 32-bit
Holding Register and the LSBs of the Holding Register will be
zeroed. See Figure 14 for details.
CIC Decimation Filter
The mixer output may be filtered with the CIC filter or it may
be routed directly to the halfband filters. The CIC filter is used
to reduce the sample rate of a wideband signal to a rate that
the halfbands and programmable filters can process, given
the maximum computation speed of PROCCLK. (See
Halfband and FIR Filter Sections for techniques to calculate
this value).
Prior to the CIC filter, the output of the mixer goes through a
barrel shifter. The shifter is used to adjust the gain in 6dB
steps to compensate for the variation in CIC filter gain with
decimation. (See Equation 6). Fine gain adjustments must
be done in the AGC Section. The shifter is controlled by the
sum of a 4-bit CIC Shift Gain word from the microprocessor
and a 3-bit gain word from the GAINADJ(2:0) pins. The three
bit value is pipelined to match the delay of the input samples.
The sum of the 3 and 4-bit shift gain words saturates at a
value of 15. Table 1 details the permissible values for the
GAINADJ(2:0) barrel shifter control, while Figure 15 shows
the permissible CIC Shift Gain values.
The CIC filter structure for the HSP50214B is fifth order; that
is it has five integrator/comb pairs. A fifth order CIC has
84dB of alias attenuation for output frequencies below 1/8
the CIC output sample rate.
FN4450 Rev 4.00
May 1, 2007
15
14
13
12
8-BIT INPUT
10-BIT INPUT
12-BIT INPUT
ALLOWABLE CIC SHIFT
GAINS ARE BELOW THE
CURVES
11
14-BIT INPUT
10
9
8
7
6
5
4
3
2
1
0
4 8 12 16 20 24 28 32 36 40 44 48 52 56 60 64
DECIMATION (R)
FIGURE 15. CIC SHIFT GAIN VALUES
The decimation factor of the CIC filter is programmed in
Control Word 0, Bits 12 - 7. The CIC Shift Gain is programmed
in Control Word 0, Bits 16-13. The CIC Bypass is set in
Control Word 0, Bit 6. When bypassing the CIC filter, the ENI
signal must be de-asserted between samples, i.e., the CLKIN
rate must be 2 fS.
TABLE 3. GAIN ADJUST CONTROL AND CIC DECIMATION
GAIN VALUE
(dB)
GAIN ADJ(2:0)
MAX. CIC
DECIMATION
0
000
32
6
001
27
12
010
24
18
011
21
24
100
18
30
101
16
36
110
12
42
111
10
CIC Gain Calculations
The gain through the CIC filter increases with increased
decimation. The programmable barrel shifter that precedes
the first integrator in the CIC is used to offset this variation.
Gain variations due to decimation should be offset using the
4-bit CIC Shift Gain word. This allows the input signal level to
be adjusted in 6dB steps to control the CIC output level.
The gain at each stage of the CIC is:
k = RN,
(EQ. 6)
where R is the decimation factor and N is the number of stages.
The input to the CIC from the mixer is 15-bits, and the bit widths
of the accumulators for the five stages in the HSP50214B are
40, 36, 32, 32, and 32, as shown in Figure 16. This limits the
maximum decimation in the CIC to 32 for a full scale input.
If R is 32, the gain through all five integrator stages is 325 = 225.
(The gain through the last four CIC stages is 220, through the
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