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HIP6018B

Advanced PWM and Dual Linear Power Control

Renesas Electronics 

HIP6018B

Application Guidelines

Soft-Start Interval

Initially, the soft-start function clamps the error amplifier’s output

of the PWM converter. After the output voltage increases to

approximately 80% of the set value, the reference input of the

error amplifier is clamped to a voltage proportional to the SS pin

voltage. Both linear outputs follow a similar start-up sequence.

The resulting output voltage sequence is shown in Figure 6.

The soft-start function controls the output voltage rate of rise to

limit the current surge at start-up. The soft-start interval is

programmed by the soft-start capacitor, CSS. Programming a

faster soft-start interval increases the peak surge current. The

peak surge current occurs during the initial output voltage rise

to 80% of the set value.

Shutdown

The PWM output does not switch until the soft-start voltage

(VSS) exceeds the oscillator’s valley voltage. Additionally, the

reference on each linear’s amplifier is clamped to the soft-start

voltage. Holding the SS pin low with an open drain or collector

signal turns off all three regulators.

The VID codes resulting in an INHIBIT as shown in Table 1

also shuts down the IC.

Layout Considerations

MOSFETs switch very fast and efficiently. The speed with which

the current transitions from one device to another causes voltage

spikes across the interconnecting impedances and parasitic circuit

elements. The voltage spikes can degrade efficiency, radiate noise

into the circuit, and lead to device over-voltage stress. Careful

component layout and printed circuit design minimizes the voltage

spikes in the converter. Consider, as an example, the turn-off

transition of the upper PWM MOSFET. Prior to turn-off, the upper

MOSFET was carrying the full load current. During the turn-off,

current stops flowing in the upper MOSFET and is picked up by the

lower MOSFET (and/or parallel Schottky diode). Any inductance in

the switched current path generates a large voltage spike during

the switching interval. Careful component selection, tight layout of

the critical components, and short, wide circuit traces minimize the

magnitude of voltage spikes. Contact Intersil for evaluation board

drawings of the component placement and printed circuit board.

There are two sets of critical components in a DC-DC converter

using a HIP6018B controller. The power components are the

most critical because they switch large amounts of energy. The

critical small signal components connect to sensitive nodes or

supply critical by-passing current.

The power components should be placed first. Locate the input

capacitors close to the power switches. Minimize the length of

the connections between the input capacitors and the power

switches. Locate the output inductor and output capacitors

between the MOSFETs and the load. Locate the PWM

controller close to the MOSFETs.

The critical small signal components include the by-pass

capacitor for VCC and the soft-start capacitor, CSS. Locate

these components close to their connecting pins on the control

IC. Minimize any leakage current paths from SS node because

the internal current source is only 11A.

+5VIN

+3.3VIN

CIN

Q3

VOUT3

VOUT2

+12V

CVCC

COCSET1

VCC GND

VIN2 OCSET1

ROCSET1

Q1

GATE3UGATE1

PHASE1

HIP6018B Q2

VOUT2 LGATE1

LOUT1 VOUT1

COUT1

CR1

SS PGND

CSS

COUT2

KEY

ISLAND ON POWER PLANE LAYER

ISLAND ON CIRCUIT PLANE LAYER

VIA CONNECTION TO GROUND PLANE

FIGURE 10. PRINTED CIRCUIT BOARD POWER PLANES AND

ISLANDS

A multi-layer printed circuit board is recommended. Figure 10

shows the connections of the critical components in the

converter. Note that capacitors CIN and COUT could each

represent numerous physical capacitors. Dedicate one solid

layer for a ground plane and make all critical component

ground connections with vias to this layer. Dedicate another

solid layer as a power plane and break this plane into smaller

islands of common voltage levels. The power plane should

support the input power and output power nodes. Use copper

filled polygons on the top and bottom circuit layers for the

phase nodes. Use the remaining printed circuit layers for small

signal wiring. The wiring traces from the control IC to the

MOSFET gate and source should be sized to carry 1A

currents. The traces for OUT2 need only be sized for 0.2A.

Locate COUT2 close to the HIP6018B IC.

PWM Controller Feedback Compensation

Both PWM controllers use voltage-mode control for output

regulation. This section highlights the design consideration for

a voltage-mode controller. Apply the methods and

considerations to both PWM controllers.

Figure 11 highlights the voltage-mode control loop for a

synchronous-rectified buck converter. The output voltage is

regulated to the reference voltage level. The reference voltage

level is the DAC output voltage for the PWM controller. The error

amplifier output (VE/A) is compared with the oscillator (OSC)

triangular wave to provide a pulse-width modulated wave with

an amplitude of VIN at the PHASE node. The PWM wave is

smoothed by the output filter (LO and CO).

FN4586 Rev 3.00

April 1, 2005

Page 10 of 15

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