PD45128163G5-A10LI-9JF Ver la hoja de datos (PDF) - Elpida Memory, Inc

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PD45128163G5-A10LI-9JF

128M-bit Synchronous DRAM 4-bank, LVTTL WTR (Wide Temperature Range)

Elpida Memory, Inc 

µPD45128441-I, 45128841-I, 45128163-I

5. Initialization

The synchronous DRAM is initialized in the power-on sequence according to the following.

(1) To stabilize internal circuits, when power is applied, a 100 µs or longer pause must precede any signal toggling.

(2) After the pause, all banks must be precharged using the Precharge command (The Precharge all banks

command is convenient).

(3) Once the precharge is completed and the minimum tRP is satisfied, the mode register can be programmed.

After the mode register set cycle, tRSC (2 CLK minimum) pause must be satisfied as well.

(4) Two or more CBR (Auto) refresh must be performed.

Remarks 1. The sequence of Mode register programming and Refresh above may be transposed.

2. CKE and DQM must be held high until the Precharge command is issued to ensure data-bus Hi-Z.

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Preliminary Data Sheet E0233N10

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