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HD74HCT137RPEL

3-to-8-line Decoder/Demultiplexer with Address Latch

Renesas Electronics 

HD74HCT137

3-to-8-line Decoder/Demultiplexer with Address Latch

REJ03D0658–0200

(Previous ADE-205-546)

Rev.2.00

Mar 30, 2006

Description

The HD74HCT137 implements a three-to-eight line decoder with latches on the three address inputs. When GL goes

from low to high, the address present at the select inputs (A, B and C) is stored in the latches. As long as GL remains

high no address changes will be recognized. Output enable controls, G1 and G2, control the state of the outputs

independently of the select or latch-enable inputs.

All of the outputs are high unless G1 is high and G2 is low. The HD74HCT137 is ideally suited for the implementation

of glitch free decoders in stored-address applications in bus oriented systems.

Features

• High Speed Operation: tpd (A, B, C to Y) = 16.5 ns typ (CL = 50 pF)

• High Output Current: Fanout of 10 LSTTL Loads

• Wide Operating Voltage: VCC = 2 V to 6 V

• Low Input Current: 1 µA max

• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)

• Ordering Information

Part Name

Package Type

Package Code

(Previous Code)

Package

Abbreviation

HD74HCT137FPEL

SOP-16 pin (JEITA)

PRSP0016DH-B

(FP-16DAV)

FP

PRSP0016DG-A

HD74HCT137RPEL SOP-16 pin (JEDEC) (FP-16DNV)

RP

Note: Please consult the sales office for the above package availability.

Taping Abbreviation

(Quantity)

EL (2,000 pcs/reel)

EL (2,500 pcs/reel)

Rev.2.00 Mar 30, 2006 page 1 of 7

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