1135IBZ Ver la hoja de datos (PDF) - Renesas Electronics
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1135IBZ Datasheet PDF : 15 Pages
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HFA1135
feedback impedance decrease at higher frequencies). At
higher gains the amplifier is more stable, so RF can be
decreased in a trade-off of stability for bandwidth.
The table below lists recommended RF values, and the
expected bandwidth, for various closed loop gains.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN
(AV)
-1
+1
+2
+5
+10
RF ()
330
1.5k
250
330
180
250
BANDWIDTH
(MHz)
290
660
360
315
200
90
Non-inverting Input Source Impedance
For best operation, the DC source impedance seen by the non-
inverting input should be 50This is especially important in
inverting gain configurations where the non-inverting input
would normally be connected directly to GND.
Pulse Undershoot and Asymmetrical Slew Rates
The HFA1135 utilizes a quasi-complementary output stage to
achieve high output current while minimizing quiescent supply
current. In this approach, a composite device replaces the
traditional PNP pulldown transistor. The composite device
switches modes after crossing 0V, resulting in added distortion
for signals swinging below ground, and an increased
undershoot on the negative portion of the output waveform
(see Figures 9, 13, and 17). This undershoot isn’t present for
small bipolar signals, or large positive signals. Another artifact
of the composite device is asymmetrical slew rates for output
signals with a negative voltage component. The slew rate
degrades as the output signal crosses through 0V (see Figures
9, 13, and 17), resulting in a slower overall negative slew rate.
Positive only signals have symmetrical slew rates as illustrated
in the large signal positive pulse response graphs (see Figures
7, 11, and 15).
PC Board Layout
This amplifier’s frequency response depends greatly on the
care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid ground
plane is a must!
Attention should be given to decoupling the power supplies. A
large value (10F) tantalum in parallel with a small value
(0.1F) chip capacitor works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the next
section.
Care must also be taken to minimize the capacitance to ground
at the amplifier’s inverting input (-IN), as this capacitance
causes gain peaking, pulse overshoot, and if large enough,
instability. To reduce this capacitance, the designer should
remove the ground plane under traces connected to -IN, and
keep connections to -IN as short as possible.
An example of a good high frequency layout is the Evaluation
Board shown in Figure 2.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line degrade the amplifier’s phase
margin resulting in frequency response peaking and possible
oscillations. In most cases, the oscillation can be avoided by
placing a resistor (RS) in series with the output prior to the
capacitance.
Figure 1 details starting points for the selection of this resistor.
The points on the curve indicate the RS and CL combinations
for the optimum bandwidth, stability, and settling time, but
experimental fine tuning is recommended. Picking a point
above or to the right of the curve yields an overdamped
response, while points below or left of the curve indicate areas
of underdamped performance.
RS and CL form a low pass network at the output, thus limiting
system bandwidth well below the amplifier bandwidth of
660MHz (AV = +1). By decreasing RS as CL increases (as
illustrated by the curves), the maximum bandwidth is obtained
without sacrificing stability. In spite of this, bandwidth still
decreases as the load capacitance increases. For example, at
AV = +1, RS = 50, CL = 20pF, the overall bandwidth is
170MHz, but the bandwidth drops to 45MHz at AV = +1, RS =
10, CL = 330pF.
50
45
40
35
30
25
20
15 AV = +1
10
5
0
0 40 80
AV = +1
AV = +2, RF = 250
120 160 200 240 280 320 360 400
LOAD CAPACITANCE (pF)
FIGURE 1. RECOMMENDED SERIES RESISTOR vs LOAD
CAPACITANCE
FN3653 Rev.6.00
January 23, 2006
Page 5 of 15
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