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CY2305ZC-1

Low Cost 3.3-V Zero Delay Buffer

Cypress Semiconductor 

CY2305, CY2309

Switching Characteristics for CY2305SI-1H and CY2309SI-1H Industrial Temperature Devices

Parameter[13]

Name

Description

Min Typ Max Unit

t1

Output frequency

30 pF load

10 pF load

tDC

Duty cycle[14] = t2 ÷ t1

Measured at 1.4 V, Fout = 66.67 MHz

tDC

Duty cycle[14] = t2 ÷ t1

Measured at 1.4 V, Fout < 50 MHz

t3

Rise time[14]

Measured between 0.8 V and 2.0 V

t4

Fall time[14]

Measured between 0.8 V and 2.0 V

t5

Output-to output skew[14] All outputs equally loaded

t6A

Delay, REF rising edge to

CLKOUT rising edge[14]

Measured at VDD/2

10

– 100 MHz

10

133.33 MHz

40.0 50.0 60.0

%

45.0 50.0 55.0

%

–

– 1.50

ns

–

– 1.50

ns

–

85 250

ps

–

– ±350 ps

t6B

t7

t8

tJ

tLOCK

Delay, REF rising edge to

CLKOUT rising edge[14]

Measured at VDD/2. Measured in PLL Bypass Mode,

CY2309 device only.

1

Device-to-device skew[14] Measured at VDD/2 on the CLKOUT pins of devices

–

Output slew rate[14]

Measured between 0.8 V and 2.0 V using Test Circuit 1

#2

Cycle-to-cycle jitter[14] Measured at 66.67 MHz, loaded outputs

–

PLL lock time[14]

Stable power supply, valid clock presented on REF

–

pin

5 8.7

– 700

–

–

60 200

– 1.0

ns

ps

V/ns

ps

ms

Switching Waveforms

Figure 4. Duty Cycle Timing

1.4 V

t1

t2

1.4 V

1.4 V

Figure 5. All Outputs Rise/Fall Time

2.0 V

OUTPUT 0.8 V

2.0 V

0.8 V

t3

t4

Figure 6. Output-Output Skew

OUTPUT

1.4 V

3.3 V

0V

OUTPUT

t5

1.4 V

Notes

13. All parameters specified with loaded outputs.

14. Parameter is guaranteed by design and characterization. Not 100% tested in production.

Document Number : 38-07140 Rev. *M

Page 8 of 19

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