CDB5503 Ver la hoja de datos (PDF) - Cirrus Logic
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CDB5503 Datasheet PDF : 54 Pages
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CS5501 CS5503
CS5501/CS5503
Internal
Status
DRDY (o)
fout =1024/CLKIN
Note 1
64/CLKIN
64/CLKIN
Analog Time 0
76/CLKIN
Digital Time 0
CS Polled
Analog Time 1
Digital Time1
CS (i)
CS5501 Hi-Z
SCLK (o)
CS5501 Hi-Z
SDATA (o)
CS5503 Hi-Z
SCLK (o)
CS5503 Hi-Z
SDATA (o)
(MSB)
(MSB)
Hi-Z
(LSB)
Hi-Z
Hi-Z
(LSB)
Hi-Z
Note: 1. There are 16 analog and digital settling periods per filter cycle (4 are shown). Data can be output in the
SSC mode in only 1 of the 8 digital time periods in each filter cycle.
Figure 4. Internal Timing
CLKIN (i)
DRDY (o)
76 CLKIN cycles
CS (i)
SDATA (o)
(MSB)
Hi-Z
B15* B14*
B19** B18**
(LSB)
B1
B0
Hi-Z
SCLK (o)
Hi-Z
Hi-Z
* CS5501
** CS5503
Figure 5. Synchronous Self-Clocking (SSC) Mode Timing
The eighth output window time overlaps the time
in which the serial output port is to be updated. If
the CS is recognized as being low when it is
polled for the eighth window time, data will be
output as normal, but the serial port will not be
updated with new data until the next serial port
update time. Under these conditions, the serial
port will experience an update rate of only 2 kSps
(CLKIN = 4.096 MHz) instead of the normal
4 kSps serial port update rate.
Upon completion of transmission of all the data
bits, the SCLK and SDATA outputs will go to a
high impedance state even with CS held low. In
the event that CS is taken high before all data bits
are output, the SDATA and SCLK outputs will
1144
DS31F54
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