CXD1914Q Ver la hoja de datos (PDF) - Sony Semiconductor
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CXD1914Q Datasheet PDF : 41 Pages
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CXD1914Q
Pin Description
Pin
Symbol
No.
1 F1
2 TVSYNC
3 OSDSW
4 ROSD
5 GOSD
6 BOSD
7 XVRST
8 SYSCLK
9 VSS1
10 XRST
11 PDCLK
12 VDD1
13 NC
14 FID
15 VSYNC
16 HSYNC
17 CSYNC
18 VSS2
19 PD0
20 PD1
21 PD2
22 PD3
23 VDD2
I/O
Description
Field ID input.
This signal indicates the field ID when resetting the vertical sync.
I
“H” indicates 1st field.
“L” indicates 2nd field.
I Test pin. Set “L”.
I Test pin. Set “L”.
I Test pin. Set “L”.
I Test pin. Set “L”.
I Test pin. Set “L”.
Vertical sync reset input in active low. This pin is pulled up. This is used for
synchronizing the phases of the external and internal vertical sync signals.
I
When XVRST= “L”, the internal digital sync generator is reset according to the
F1 status.
System clock input.
I
To generate the correct subcarrier frequency, precise 27 MHz is required.
— Digital ground.
System reset input in active low.
I
Set “L” for 40 clocks (SYSCLK) or more during power-on reset.
Pixel data clock signal output for 13.5 MHz.
O A 13.5 MHz signal frequency divided from the system clock (SYSCLK) is output
and used as the clock signal when 16-bit pixel data is input.
— Digital power supply.
— Not connected inside the IC.
Field ID output.
When control register bit “FIDS” = “1”, “L” indicates 1st field and “H” indicates
O
2nd field. When control register bit “FIDS” = “0”, “H” indicates 1st field and “L”
indicates 2nd field.
O Vertical sync signal output.
O Horizontal sync signal output.
O Composite SYNC output when using RGB output.
— Digital ground.
I
8-bit pixel data inputs, or lower 8-bit pixel data inputs when 16-bit pixel data is
I input. [PD0 to 7]
When control register bit “PIF MODE” = “0”, these are multiplexed Y, Cb, and
I Cr signal inputs. When control register bit “PIF MODE” = “1”, these are Y
signal inputs.
I
— Digital power supply.
—3—
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