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MAX2460

900MHz Image-Reject Transceivers

Maxim Integrated 

900MHz Image-Reject Transceivers

Pin Description

PIN

NAME

FUNCTION

1

VCC

Supply-Voltage Input for Master Bias Cell. Bypass with a 47pF low-inductance capacitor and 0.1µF to

GND (pin 28, if possible).

2

CAP1

Receive Bias Compensation Pin. Bypass with a 47pF low-inductance capacitor and 0.01µF to GND.

Do not make any other connections to this pin.

3

RXOUT Single-Ended, 330Ω IF Output. AC couple to this pin.

Transmit Gain-Control Input. Connect to VCC for highest gain and best temperature stability. When

4

TXGAIN driven with a control voltage, the IF buffer gain can be adjusted over a 36dB range (see Typical

Operating Characteristics).

5

RXIN

Receiver RF Input, single-ended. The input match shown in Figure 1 maintains an input VSWR of better

than 2:1 from 902MHz to 928MHz.

6

VCC

Supply Voltage Input for Receive Low-Noise Amplifier. Bypass with a 47pF low-inductance capacitor to

GND (pin 7 if possible).

7

GND

Ground Connection for Receive Low-Noise Amplifier

8

GND

Ground Connection for Signal-Path Blocks, except LNA

9

TXOUT

PA Predriver Output. See Figure 1 for an example matching network, which provides better than 2:1

VSWR from 902MHz to 928MHz.

Low-Noise Amplifier Gain-Control Input. Drive this pin high for maximum gain. When LNAGAIN is pulled

10

LNAGAIN

low, the LNA is capacitively bypassed and the supply current is reduced by 4.5mA. This pin can also be

driven with an analog voltage to adjust the LNA gain in intermediate states. Refer to the Receiver Gain

vs. LNAGAIN Voltage graph in the Typical Operating Characteristics, as well as Table 1.

11

VCC

Supply Voltage Input for Signal-Path Blocks, except LNA. Bypass with a 47pF low-inductance capacitor

and 0.01µF to GND (pin 8, if possible).

12

TXIN

Transmitter IF Input, 330Ω, single-ended. AC couple to this pin.

13

N.C.

No Connect. Not internally connected.

14

CAP2

Transmit Bias Compensation Pin. Bypass with a 47pF low-inductance capacitor and 0.01µF to GND.

Do not make any other connections to this pin.

15

TXON

Driving TXON with a logic high enables the transmit IF variable-gain amplifier, upconverter mixer, and PA

predriver. VCOON must also be high.

16

RXON

Driving RXON with a logic high enables the LNA, receive mixer, and IF output buffer. VCOON must also

be high.

17

VCOON

Driving VCOON with a logic high turns on the VCO, phase shifters, VCO buffers, and prescaler. The

prescaler can be selectively disabled by floating the PREGND pin.

Driving DIV1 with a logic high disables the divide-by-64/65 prescaler and connects the PREOUT pin

18

DIV1

directly to an oscillator buffer amplifier, which outputs -8dBm into a 50Ω load. Tie DIV1 low for divide-by-

64/65 operation. Pull this pin low when in shutdown to minimize off current.

19

MOD

Modulus Control for the Divide-by-64/65 Prescaler: high = divide-by-64, low = divide-by-65. Note that

the DIV1 pin must be at logic low when using the prescaler mode.

Ground connection for the Prescaler. Tie PREGND to ground for normal operation. Leave floating to

20

PREGND disable the prescaler and the output buffer. Tie MOD and DIV1 to ground and leave PREOUT floating

when disabling the prescaler.

Prescaler/Oscillator Buffer Output. In divide-by-64/65 mode (DIV1 = low), the output level is 500mVp-p

21

PREOUT into a high-impedance load. In divide-by-1 mode (DIV1 = high), this output delivers -8dBm into a 50Ω

load. AC couple to this pin.

8 _______________________________________________________________________________________

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