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74ALVCH16501 Datasheet PDF : 18 Pages
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NXP Semiconductors
74ALVCH16501
18-bit universal bus transceiver; 3-state
5. Pinning information
5.1 Pinning
OEAB 1
LEAB 2
A0 3
GND 4
A1 5
A2 6
VCC 7
A3 8
A4 9
A5 10
GND 11
A6 12
A7 13
A8 14
A9 15
A10 16
A11 17
GND 18
A12 19
A13 20
A14 21
VCC 22
A15 23
A16 24
GND 25
A17 26
OEBA 27
LEBA 28
Fig 5. Pin configuration
74ALVCH16501
56 GND
55 CPAB
54 B0
53 GND
52 B1
51 B2
50 VCC
49 B3
48 B4
47 B5
46 GND
45 B6
44 B7
43 B8
42 B9
41 B10
40 B11
39 GND
38 B12
37 B13
36 B14
35 VCC
34 B15
33 B16
32 GND
31 B17
30 CPBA
29 GND
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5.2 Pin description
Table 2. Pin description
Symbol
Pin
OEAB
1
LEAB
2
A0 to A17
3, 5, 6, 8, 9, 10, 12, 13, 14, 15, 16, 17, 19, 20, 21, 23, 24, 26
GND
4, 11, 18, 25, 29, 32, 39, 46, 53, 56
VCC
OEBA
7, 22, 35, 50
27
LEBA
28
Description
output enable A-to-B input
latch enable A-to-B input
data inputs or outputs
ground (0 V)
positive supply voltage
output enable B-to-A
latch enable B-to-A
74ALVCH16501_3
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 03 — 2 April 2010
© NXP B.V. 2010. All rights reserved.
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