HT1627 Ver la hoja de datos (PDF) - Holtek Semiconductor

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fabricante

HT1627

RAM Mapping 64
16 LCD Controller for I/O μC

Holtek Semiconductor 

W R ,R D 90%

C lo c k

50%

10%

tf

tr

tC L K

tC L K

Figure 1

CS

W R ,R D

C lo c k

50%

tsu 1

tC S

th 1

50%

F IR S T

C lo c k

LA S T

C lo c k

Figure 3

DB

V DD

G N D W R ,R D

C lo c k

V DD

GND

V DD

GND

V A L ID D A T A

50%

ts u

th

50%

Figure 2

HT1627

V DD

GND

V DD

GND

Functional Description

Display memory - RAM structure

The static display RAM is organized into 256*4

bits and stores the display data. The contents of

the RAM are directly mapped to the contents of

the LCD driver. Data in the RAM can be ac-

cessed by the READ, WRITE and READ-MOD-

IFY-WRITE commands. The following is a map-

ping from the RAM to the LCD patterns.

C O M 15 C O M 14 C O M 13 C O M 12

Time base and Watchdog Timer - WDT

The time base generator and WDT share the

same divided (/256) counter. TIMER DIS/EN/CLR

, WDT DIS/EN/CLR and IRQ EN/DIS are inde-

pendent from each other. Once the WDT

time-out occurs, the IRQ pin will remain at

logic low level until the CLR WDT or the IRQ

DIS command is issued.

COM 3 COM 2 COM 1 COM 0

SEG 0

3

0

SEG 1

7

4

SEG 2

11

SEG 3

15

8

12

A d d r e s s 8 B its

(A 7 , A 6 , ...., A 0 )

S E G 63

255

252

A ddr

D3

D2

D1

D0

D a ta

A ddr

D3

D2

D1

D0

D a ta

D a ta 4 B its

(D 3 , D 2 , D 1 , D 0 )

RAM mapping

8

April 21, 2000

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