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78Q8430

10/100 Ethernet MAC and PHY

Teridian Semiconductor Corporation 

78Q8430 Data Sheet

4.5.3 100Base-TX Receiver

Table 18: MII 100Base-TX Receiver Timing

Parameter

Signal Detect Assertion Threshold

Signal Detect De-assertion Threshold

Differential Input Resistance

Jitter Tolerance (pk-pk)

Baseline Wander Tracking

Signal Detect Assertion Time

Signal Detect De-assertion Time

Conditions

Not tested

Not tested

Min

Nom

600

700

300

350

–

20

4

–

-75

–

–

–

–

–

DS_8430_001

Max

800

400

–

–

+75

1000

4

Unit

mVppd

mVppd

kΩ

ns

%

µs

µs

4.5.4 10Base-T Transmitter

Table 19: MII 10Base-T Transmitter Timing

Parameter

Conditions

Min Nom Max Unit

Peak Differential Output Signal All data patterns

(see note below)

2.2

–

2.8

V

Harmonic Content

(dB below fundamental)

Any harmonic

All ones data

Not tested

27

–

–

dB

Link Pulse Width

–

100

–

ns

Start-of-Idle Pulse Width

Last bit 0

Last bit 1

–

300

–

ns

–

350

–

ns

Note: The Manchester-encoded data pulses, the link pulse and the start-of-idle pulse are tested against

the templates and using the procedures found in Clause 14 of IEEE 802.3. Measured at the line side of

the transformer. Test Condition: Transformer P/N: TLA-6T103. Line Termination: 100 Ω±1%

4.5.5 10Base-T Transmitter (Informative)

Table 20: MII 10Base-T Transmitter (Informative)

Parameter

Conditions

Min Nom Max Unit

Output Return Loss

15

–

–

dB

Output Impedance Balance

1 MHz < freq < 20 MHz

Peak Common-mode Output Voltage

29

−

17

log

f

10



–

–

–

–

dB

50 mV

Common-mode Rejection

15 VPK, 10.1 MHz sine

–

wave applied to transmitter

common-mode. All data

sequences.

–

100 mV

Common-mode Rejection Jitter

15 VPK, 10.1 MHz sine

–

wave applied to transmitter

common-mode. All data

sequences.

–

1

ns

Note: The specifications in the preceding table are included for information only. They are mainly a

function of the external transformer and termination resistors used for measurements

20

Rev. 1.2

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