78Q8430 Ver la hoja de datos (PDF) - Teridian Semiconductor Corporation

Número de pieza

componentes Descripción

Lista de partido

78Q8430

10/100 Ethernet MAC and PHY

Teridian Semiconductor Corporation 

DS_8430_001

78Q8430 Data Sheet

1 Introduction

The Teridian 78Q8430 is a single chip 10Base-T/100Base-TX capable Fast Ethernet Media Access

Controller (MAC) and Physical Layer (PHY) transceiver. The device is optimized for video applications,

such as the Set Top Box (STB), and easily interfaces to available STB core processors, such as the

STi5100, STi5516, STi5514, ARM™ and Intel® based processors. The 78Q8430 is compliant with

applicable IEEE-802.3 standards. MAC and PHY configuration and status registers are provided as

specified by IEEE-802.3u.

The 78Q8430 operates over Category-5 Unshielded Twisted Pair (Cat-5 UTP) cabling in 100Base-TX

applications and over Cat-3 UTP in 10Base-T applications requiring only a dual 1:1 isolation transformer

interface to the copper media.

The Ethernet MAC section makes use of a 32 kB deep on-chip SRAM FIFO packet memory to adaptively buffer

transmit and receive data. SRAM memory can be dynamically allocated to either the transmit queues or the

receive queues as required to optimize throughput.

The host processor accesses the FIFO(s) using a simple asynchronous pseudo-SRAM like host bus interface.

A 32 bit wide bus is provided; the bus width can be pin-configured for 8-bit, 16-bit or 32-bit bus width at boot-up.

Big endian, little endian and mixed endian options are available in 32-bit operation; little endian is available for

16-bit operation. Different End-in variations are supported through internal circuitry with minimal user

intervention required.

The MAC interface logic may assert MEMWAIT during bus transactions, requesting wait states from the host

while critical internal data transfer completes. The MAC provides both half duplex and full duplex operation, as

well as support for full duplex flow control. Complete, portable device drivers for Linux®, OS20 and VxWorks®

are available.

The 78Q8430 operates from a single 3.3 V supply. Power down modes and power saving modes are

available. The 78Q8430 defaults to use an on-chip crystal oscillator. In this mode, a 25 MHz reference

crystal is connected between the XTLP and XTLN pins. Alternatively, an externally generated 25 MHz

clock can be connected to the XTLP pin. The chip will automatically configure itself to use the external

clock. In this mode of operation, a crystal is not required.

1.1 Systems Applications

Figure 1 presents an overview of the 78Q8430 in a block diagram.

8-bit/16-bit/32-bit

System Bus

Configuration

EEPROM Interface

(Optional)

JTAG Interface

TERIDIAN

78Q8430

Single Chip

10/100 Ethernet

Controller

LED

Link (Programmable)

LED

Activity (Programmable)

RJ45

1:1

Transformer

CAT 5

Cable

Figure 1: 78Q8430 Block Diagram

Rev. 1.2

7

Share Link: