MK2049-36 Ver la hoja de datos (PDF) - Integrated Circuit Systems
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MK2049-36 Datasheet PDF : 10 Pages
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PRELIMINARY INFORMATION
MK2049-36
3.3 V Communications Clock PLL
Pin Assignment
FS1 1
X2 2
X1 3
VDD 4
FCAP 5
VDD 6
GND 7
CLK 8
CLK/2 9
8K 10
20 FS0
19 RES
18 CAP2
17 GND
16 CAP1
15 VDD
14 GND
13 ICLK
12 FS3
11 FS2
20 pin (300 mil) SOIC
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
FS1
X2
X1
VDD
FCAP
VDD
GND
CLK
CLK/2
8K
FS2
FS3
ICLK
GND
VDD
CAP1
GND
CAP2
RES
FS0
Type Description
I Frequency Select 1. Determines CLK input/outputs per tables on page 4.
XO Crystal connection. Connect to a MHz crystal as shown in the tables on page 4.
XI Crystal connection. Connect to a MHz crystal as shown in the tables on page 4.
P Connect to +3.3V.
- Filter Capacitor. Connect a 1000 pF ceramic capacitor to ground.
P Connect to +3.3V.
P Connect to ground.
O Clock output determined by status of FS3:0 per tables on page 4.
O Clock output determined by status of FS3:0 per tables on page 4. Always 1/2 of CLK.
O Recovered 8 kHz clock output.
I Frequency Select 2. Determines CLK input/outputs per tables on page 4.
I Frequency Select 3. Determines CLK input/outputs per tables on page 4.
I Input clock connection. Connect to 8 kHz backplane or MHz clock.
P Connect to ground.
P Connect to +3.3V.
LF Connect the loop filter ceramic capacitors and resistor between this pin and CAP2.
P Connect to ground.
LF Connect the loop filter ceramic capacitors and resistor between this pin and CAP1.
- Connect a 10-200kΩ resistor to ground. Contact ICS applications dept. at 408-297-1201 for the recommended value for your app.
I Frequency Select 0. Determines CLK input/outputs per tables on page 4.
Type: XI, XO = crystal connections, I = Input, O = output, P = power supply connection, LF = loop filter
connections
MDS 2049-36 A
2
Revision 120400
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel• www.icst.com
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