MC145220DT Ver la hoja de datos (PDF) - Freescale Semiconductor
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MC145220DT Datasheet PDF : 27 Pages
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Freescale Semiconductor, Inc.
PDout/φR, PDouti/φRi
Single–Ended Phase/Frequency Detector Outputs
(Pins 4 and 17)
When the C2 bits in the C or Ci registers are low, these
pins are independently configured as single–ended outputs
PDout or PDouti, respectively. As such, each pin is a three–
state current–source/sink output for use as a loop error sig-
nal when combined with an external low–pass filter. The
phase/frequency detector is characterized by a linear trans-
fer function. The operation of the phase/frequency detector is
described below and is shown in Figure 17.
POL bit (C0) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR: current–
sinking pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR: current–
sourcing pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
POL bit (C0) = high
Frequency of fV > fR or Phase of fV Leading fR: current–
sourcing pulses from a floating state
Frequency of fV < fR or Phase of fV Lagging fR: current–
sinking pulses from a floating state
Frequency and Phase of fV = fR: essentially a floating
state; voltage at pin determined by loop filter
These outputs can be enabled, disabled, and inverted via
the C and Ci registers. If desired, these pins can be forced to
the floating state by utilization of the standby feature in the C
or Ci registers (bit C6). This is a patented feature.
The phase detector gain is controllable by bits C4 and C5:
gain (in amps per radian) = PDout current in amps divided
by 2π.
These outputs can be enabled, disabled, or interchanged
via C register bits C6 or C0. This is a patented feature. Note
that when disabled in standby, these outputs are forced to
their rest condition (high state). See Figure 14.
The φR and φV output signals swing from approximately
GND to V+.
LD and LDi
Lock Detector Outputs (Pins 3 and 18)
Each output is essentially at a high–impedance state with
very narrow low–going pulses of a few nanoseconds when
the respective loop is locked (fR and fV of the same phase
and frequency). The output pulses low when fV and fR are
out of phase or different frequencies. LD is the logical AND-
ing of φR and φV, while LDi is the logical ANDing of φRi and
φVi. See Figure 17.
Upon power up, on–chip initialization circuitry forces LD
and LDi to the high–impedance state. These pins are low
during standby. If unused, LD should be tied to GND and LDi
should be tied to GNDi.
These outputs have open–drain N–channel MOSFET driv-
ers. This facilitates a wired–OR function. See Figure 21.
Rx/φV and Rxi/φVi
External Current Setting Resistors (Pins 5 and 16)
When the C2 bits in the C or Ci registers are low, these two
pins are independently configured as current setting pins Rx
or Rxi, respectively. As such, resistors tied between each of
these pins and GND and GNDi, in conjunction with bits C4
and C5 in the C and Ci registers, determine the amount of
current that the PDout pins sink and source. When bits C4
and C5 are both set high, the maximum current is obtained;
see Table 2 for other values of current.
PDout /φR, Rx/ φV and PDouti/φRi, Rxi/φVi
Double–Ended Phase/Frequency Detector Outputs
(Pins 4, 5 and 17, 16)
When the C2 bits in the C or Ci registers are high, these
two pairs of pins are independently configured as double–
ended outputs φR, φV or φRi, φVi, respectively. As such,
these outputs can be combined externally to generate a loop
error signal. Through use of a Motorola patented technique,
the detector’s dead zone has been eliminated. Therefore, the
phase/frequency detector is characterized by a linear trans-
fer function. The operation of the phase/frequency detectors
are described below and are shown in Figure 17.
POL bit (C0) in the C register = low (see Figure 14)
Frequency of fV > fR or Phase of fV Leading fR: φV =
negative pulses, φR = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φV =
essentially high, φR = negative pulses
Frequency and Phase of fV = fR: φV and φR remain
essentially high, except for a small minimum time period
when both pulse low in phase
POL bit (C0) = high
Frequency of fV > fR or Phase of fV Leading fR: φR =
negative pulses, φV = essentially high
Frequency of fV < fR or Phase of fV Lagging fR: φR =
essentially high, φV = negative pulses
Frequency and Phase of fV = fR: φV and φR remain
essentially high, except for a small minimum time period
when both pulse low in phase
Table 2. PDout or PDout′ Current
C5
C4
Current
0
0
5%
0
1
50%
1
0
80%
1
1
100%
The formula for determining the value of Rx or Rxi is as
follows.
V1 – V2
Rx = I
where Rx is the value of external resistor in ohms, V1 is the
supply voltage, V2 is 1.5 V for a reference current through Rx
of 100 µA or 1.745 V for a reference current of 200 µA, and I
is the reference current flowing through Rx or Rxi.
The reference current flowing through Rx or Rx′ is multi-
plied by a factor of approximately 10 (in the 100% current
mode) and delivered by the PDout or PDout′ pin, respectively.
To achieve a maximum phase detector output current of
1 mA, the resistor should be about 15 kΩ when a 3 V supply
is employed. See Table 3.
Supply
Voltage
3V
5V
Table 3. Rx Values
PDout or PDout′
Current in
Rx
100% Mode
15 kΩ
16 kΩ
1 mA
2 mA
MOTOROLA WIRELESS SEMICONDUCTOR
SOLUTIONS DEVICE DATA For More Information On This Product,
Go to: www.freescale.com
MC145220
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