MAX3674 Ver la hoja de datos (PDF) - Microsemi Corporation
Número de pieza
componentes Descripción
Lista de partido
MAX3674 Datasheet PDF : 20 Pages
| |||
High-Performance, Dual-Output,
Network Clock Synthesizer
PIN
1, 4, 13, 30,
34, 36, 42
2
3, 8, 19, 27,
31, 37
NAME
VCC
BYPASS
GND
I/O
Supply
Input
Supply
5
VCC_PLL
Supply
6
7
9, 10
11, 12
14–18,
20–24
REF_SEL
REF_CLK
CLK_STOPA,
CLK_STOPB
XTAL1,
XTAL2
M[9:0]
25
TEST_EN
26
28
29
32
33
35
38, 39, 40
41
43
44
LOCK
QB
QB
QA
QA
NB
NA[2:0]
PLOAD
MR
SDA
45
46, 47
48
SCL
ADR[1:0]
P
Input
Input
Input
Input
Input
Input
Output
Output
Output
Input
Input
Input
Input
Input/
Output
Input
Input
Input
Pin Description
TYPE
FUNCTION
VCC
LVCMOS
Positive Power Supply
Selects the Static Circuit Bypass Mode
Ground Ground
VCC
LVCMOS
LVCMOS
LVCMOS
Positive Power Supply for the PLL (Analog Power Supply). It is
recommended to use an external passive filter for the supply pin
VCC_PLL. See Figure 5.
Selects Reference Clock Input
PLL External Reference Clock Input
Output Qx Disable in Logic-Low State
Analog Crystal Oscillator Interface
LVCMOS PLL Feedback-Divider Configuration
LVCMOS
LVCMOS
Factory Test Mode Enable. This pin must be connected to GND in
all applications of the device.
PLL Lock Indicator
LVPECL Channel B Differential Clock Output
LVPECL Channel A Differential Clock Output
LVCMOS
LVCMOS
LVCMOS
LVCMOS
LVCMOS/
Open Drain
LVCMOS
LVCMOS
LVCMOS
PLL Postdivider Configuration for Output QB
PLL Postdivider Configuration for Output QA and QB
Selects the Programming Interface for Parallel or I2C
Device Master Reset
I2C Data
I2C Clock
Selectable Two Bits of the I2C Slave Address
PLL Predivider Configuration
_______________________________________________________________________________________ 7
Share Link: 