U5020M-MFPG3 Ver la hoja de datos (PDF) - Atmel Corporation
Número de pieza
componentes Descripción
Lista de partido
U5020M-MFPG3 Datasheet PDF : 10 Pages
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U5020M
3. Pin Description
Pin
Symbol Function
1
TM
Test must not be connected
2
3 to 8
9
TM
WAKE-UP
ENA
Test must be connected to GND
Wake-up inputs (pull-down resistor)
There are six digitally debounced wake-up inputs. During the long trigger mode each signal slope at the
inputs initiates a reset pulse at pin 10.
Enable output (push-pull)
It is used for the control of peripheral components. It is activated after the processor triggers three times
correctly.
Reset output (open drain)
10
RESET Resets the processor in the case of a trigger error or if a wake-up pulse occurs during the long watchdog
period.
11
TRIG
Trigger input (pull-up resistor)
It is connected to the microprocessor’s trigger signal.
12
MODE
Mode input (pull-up resistor)
The processor’s mode signal initiates the switchover between the long and the short watchdog time.
13
VDD
Supply voltage
14
GND
Ground, reference voltage
15
OSC
RC oscillator
16
TS
Time switch input
Programming pin to select different time durations for the long watchdog time.
4. Functional Description
4.1 Supply, Pin 13
The U5020M requires a stabilized supply voltage VDD = 5 V ±5% to comply with its electrical
characteristics.
An external buffer capacitor of C = 10 nF may be connected between pin 13 and GND.
4.2 RC Oscillator, Pin 15
The clock frequency, f, can be adjusted by the components R1 and C1 according to the formula:
f = 1--
t
where t = 1.35 + 1.57 R1 (C1 + 0.01)
R1 in kΩ, C1 in nF and t in µs
The clock frequency determines all time periods of the logic part as shown in the table “Electrical
Characteristics” under the subheading “Timing” on page 8. With an appropriate component
selection, the clock frequency, f, is nearly independent of the supply voltage as shown in Figure
4-1 on page 4.
Frequency tolerance ∆fmax = 10% with R1 ±1%, C1 = ±5%
3
4755B–AUTO–11/05
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