A62S6308A Ver la hoja de datos (PDF) - AMIC Technology

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Lista de partido

A62S6308A

64K X 8 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise and Fall Time

Input and Output Timing Reference Levels

Output Load

0.4V to 2.4V

5 ns

1.5V

See Figures 1 and 2

A62S6308A Series

TTL

TTL

CL

30pF

CL

5pF

* Including scope and jig.

* Including scope and jig.

Figure 1. Output Load

Figure 2. Output Load for tCLZ1,

tCLZ2, tOHZ, tOLZ, tCHZ1,

tCHZ2, tWHZ, and tOW

Data Retention Characteristics (TA = 0°C to +70°C or -40°C to +85°C)

Symbol

Parameter

Min. Max. Unit

Conditions

VDR1

VDR2

VCC for Data Retention

2.0

3.6

2.0

3.6

V

CE1 ≥ VCC - 0.2V

V CE2 ≤ 0.2V

ICCDR1

ICCDR2

Data Retention Current

-

1*

-

1*

tCDR

Chip Disable to Data Retention Time

0

-

tR

Operation Recovery Time

tRC

-

tVR

VCC Rise Time from Data Retention Voltage

to Operating Voltage

5

-

* A62S6308A-55S/70S

A62S6308A-55SU/70SU

ICCDR: Max. 1μA at TA = 0°C to +40°C

ICCDR: Max. 1μA at TA = 0°C to +40°C

VCC = 2.0V

μA CE1 ≥ VCC - 0.2V

VIN ≥ 0V

VCC = 2.0V

μA

CE2 ≤ 0.2V

VIN ≥ 0V

ns

ns See Retention Waveform

ms

PRELIMINARY (May, 2011, Version 0.0)

10

AMIC Technology, Corp.

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