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ICS650-41

SPREAD SPECTRUM CLOCK SYNTHESIZER

Integrated Device Technology 

ICS650-41

SPREAD SPECTRUM CLOCK SYNTHESIZER

Timing Diagrams

CLOCK SYNTHESIZER

VDDs

0.01µF

DUT

GND

Outputs

CLOAD

C lo ck

t1

t2

VDDO

50% of VDDO

0V

Figure 1: Test and Measurement Setup

t3

Clock

Output

t4

VDDO

80% of VDDO

20% of VDDO

0V

Figure 3: Rise and Fall Time Definitions

Figure 2: Duty Cycle Definitions

VDD

Power Up

T im e

VCO Ramp

Time

PLL Locked

0V

VDD

0V

0 ms

4 ms

10 ms

Figure 4: Power Up and PLL Lock Timing

PDTS

CLK

O utpu ts

1.25 V

1%

t EN

t DIS

1.25 V

VOH

0V

Figure 5: PDTS to Stable Clock Output Timing

Mean value

Absolute jitter

tJA

(p - p)

Figure 6: Short Term Jitter Definition

IDT™ / ICS™ SPREAD SPECTRUM CLOCK SYNTHESIZER

8

ICS650-41 REV G 102709

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