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FDC37B727-NS

128 Pin Enhanced Super I/O Controller with ACPI Support

SMSC -> Microchip 

FUNCTIONAL DESCRIPTION

SUPER I/O REGISTERS

HOST PROCESSOR INTERFACE

The address map, shown below in Table 1, shows

the addresses of the different blocks of the Super

I/O immediately after power up. The base

addresses of the FDC, serial and parallel ports can

be moved via the configuration registers. Some

addresses are used to access more than one

register.

The host processor communicates with the

FDC37B72x through a series of read/write

registers. The port addresses for these registers

are shown in Table 1. Register access is

accomplished through programmed I/O or DMA

transfers. All registers are 8 bits wide. All host

interface output buffers are capable of sinking a

minimum of 12 mA.

TABLE 4 - SUPER I/O BLOCK ADDRESSES

LOGICAL

ADDRESS

BLOCK NAME

DEVICE

Base+(0-5) and +(7)

Floppy Disk

0

Parallel Port

3

Base+(0-3)

SPP

Base+(0-7)

EPP

Base+(0-3), +(400-402)

ECP

Base+(0-7), +(400-402)

ECP+EPP+SPP

Base+(0-7)

Serial Port Com 1

4

Base+(0-7)

Serial Port Com 2

5

60, 64

KYBD

7

Base + (0-17h)

ACPI, PME, SMI

A

Base + (0-1)

Configuration

NOTES

IR Support

Note 1: Refer to the configuration register descriptions for setting the base address

14

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