TQ2060 Ver la hoja de datos (PDF) - TriQuint Semiconductor

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TQ2060

High-Frequency Clock Generator

TriQuint Semiconductor 

TQ2060

Figure 2. Simplified Block Diagram

REFCLK

Phase

Detector

VCO

÷ 10

(35MHz to

50 MHz)

MUX ÷ 2

MUX

TESTIN

TEST1

TEST2

Control

QN (350 MHz

to

Q 500 MHz)

Table 1. Mode Selection

Mode

TEST1

TEST2

TESTIN 1

REFCLK

1(Test)

2 (Test)

3 (Test)

4 (Bypass)

5 (Normal

0

0

fTESTCLK

“don’t care”

0

1

“don’t care”

“don't care”

1

0

1

1

1

1

fTESTCLK

0

1

“don't care”

fREFCLK

fREFCLK

Notes: 1. In modes 1 and 3, TESTIN may be used to bypass the PLL. A clock input at TESTIN will be divided as shown.

2. REFCLK = 35 MHz to 50 MHz.

3. Q, QN = 350 MHz to 500 MHz.

Q, QN

fREFCLK2 ÷ 20

0, 1

fTESTCLK ÷ 2

fREFCLK

10 x fREFCLK3

Figure 3. Recommended Layout

(Not to scale)

REFCLK

(from TTLoscillator)

GND

0.1 µF

(From TTL Oscillator)

Pin 1 VDD

GND

0.1 µF

VDD

GND

Q 50 OHMS

QN

VDD

0.1 µF

GND

2

For additional information and latest specifications, see our website: www.triquint.com

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