MB88152A-112 Ver la hoja de datos (PDF) - Cypress Semiconductor

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MB88152A-112

Spread Spectrum Clock Generator

Cypress Semiconductor 

16. Lock-up Time

VDD

XIN

Setting pin

SEL

FREQ1/XENS

FREQ0/FREQ

CKOUT

3.0 V

Internal clock

stabilization wait time

VIH

tLK

(lock-up time )

MB88152A

If the setting pin is fixed at the “H” or “L” level, the maximum time after the power is turned on until the set clock signal is output from

CKOUT pin is (the stabilization wait time of input clock to XIN pin) + (the lock-up time “tLK”). For the input clock stabilization time,

check the characteristics of the resonator or oscillator used.

XIN

VIH

XENS

CKOUT

tLK

(lock-up time )

VIL

tLK

(lock-up time )

For modulation enable control using the XENS pin during normal operation, the set clock signal is output from

CKOUT pin at most the lock-up time (tLK) after the level at the XENS pin is determined.

Note: When the pin setting is changed, the CKOUT pin output clock stabilization time is required. Until the output clock signal becomes

stable, the output frequency, output clock duty cycle, modulation period, and cycle-cycle jitter cannot be guaranteed. It is therefore

advisable to perform processing such as cancelling a reset of the device at the succeeding stage after the lock-up time.

Document Number: 002-08308 Rev. *B

Page 17 of 24

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