EMC6D102-CZC-TR(2006) Ver la hoja de datos (PDF) - SMSC -> Microchip

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EMC6D102-CZC-TR
(Rev.:2006)

Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features

SMSC -> Microchip 

Fan Control Device with Hardware Monitoring and Acoustic Noise Reduction Features

Datasheet

Note:

The INT# signal is an alternate function on the PWM2 and TACH3 pins. The EMC6D102 device

will respond to the SMBus Alert Response address even if the INT# signal is not selected as

the alternate function on one of these pins as long as the following conditions exist: the INTEN

bit (register 7Ch bit 2) is set, an individual status bit is set in one of the interrupt status

registers, and the corresponding group enable bit is set. Each interrupt event must be enabled

into the interrupt status registers, and the status bits must be enabled onto the INT# signal via

the group enable bits for each type of event (i.e., temperature, voltage and fan). See the

section titled Interrupt Status Registers on page 21.

SMSC EMC6D102

17

DATASHEET

Revision 0.4 (06-15-06)

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