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CMX635

ISDN Subscriber Processor

MX-COM Inc  

ISDN subscriber Processor

Section

Page 2 of 88

CONTENTS

CMX635 Advance Information

Page

1 Block Diagrams ...........................................................................................................................................5

1.1 Functional Block Diagram ....................................................................................................5

1.2 Analog Block Diagram..........................................................................................................6

2 Signal List.....................................................................................................................................................7

2.1 Pin numbers .........................................................................................................................7

2.2 Pin description......................................................................................................................9

3 External Components ...............................................................................................................................11

3.1 Component Values.............................................................................................................12

3.2 Equivalent Analog Input/Output Circuits.............................................................................13

4 Functional Description..............................................................................................................................14

4.1 The ST interface and Digital Phase Locked Loop ..............................................................15

4.2 The HDLC Controllers and FIFOs ......................................................................................16

4.3 The IOM Interface ..............................................................................................................17

4.4 The G.711 Codec and Analog Gain Path...........................................................................18

4.5 The Tone Generator and Tone Decoder ............................................................................19

4.6 The Channel Routing Block ...............................................................................................19

4.7 Speaker Phone Functions ..................................................................................................20

4.8 The Processor Interface, Top Level Status and Power Control .........................................20

5 Programming Guide. .................................................................................................................................21

5.1 Interrupt Structure ..............................................................................................................21

5.2 CMX635 Register Definition and Description .....................................................................23

5.2.1 ST Interface Block .................................................................................................................23

5.2.1.1 ST Control Register.........................................................................................................24

5.2.1.2 ST Set-Up Register .........................................................................................................24

5.2.1.3 ST Interrupt Register/Interrupt Mask Register ................................................................25

5.2.1.4 ST Status Register ..........................................................................................................25

5.2.1.5 ST State Machine Register/ State Machine Mask Register............................................26

5.2.1.6 Multi-Frame S Register ...................................................................................................27

5.2.1.7 Multi-Frame Q Register...................................................................................................27

5.2.1.8 Multi-Frame Status Register/ Mask Register ..................................................................28

5.2.1.9 Multi-Frame S Bit Counter...............................................................................................29

5.2.2 Data Routing Block................................................................................................................29

5.2.3 HDLC FIFO Control...............................................................................................................31

5.2.3.1 Base Address Registers..................................................................................................31

5.2.3.2 Read/Write Ports.............................................................................................................31

5.2.3.3 Fifo Clear Register ..........................................................................................................32

5.2.3.4 Status and Mask Registers .............................................................................................32

5.2.4 HDLC Rx Channel Control ....................................................................................................33

5.2.4.1 Rx Mode Register ...........................................................................................................33

5.2.4.2 Address Matching Control registers................................................................................34

2001 MX-COM, Inc.

www.mxcom.com Tel: 800 638 5577 336 744 5050 Fax: 336 744 5054

Doc. # 20480225.002

4800 Bethania Station Road, Winston-Salem, NC 27105-1201 USA All trademarks and service marks are held by their respective companies.

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