M12L128324A2E Ver la hoja de datos (PDF) - [Elite Semiconductor Memory Technology Inc.

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M12L128324A2E

1M x 32 Bit x 4 Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

(Preliminary)

M12L128324A (2E)

DC CHARACTERISTICS

Recommended operating condition unless otherwise noted，TA = 0 to 70 °C

Parameter

Symbol

Operating Current

(One Bank Active)

ICC1

Precharge Standby Current ICC2P

in power-down mode

ICC2PS

Precharge Standby Current

in non power-down mode

ICC2N

ICC2NS

Active Standby Current

in power-down mode

ICC3P

ICC3PS

Active Standby Current

in non power-down mode

(One Bank Active)

ICC3N

ICC3NS

Test Condition

Burst Length = 1

tRC ≥ tRC(min)

IOL = 0 mA

CKE ≤ VIL(max), tCC = 10ns

CKE & CLK ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

Input signals are changed one time during 20ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

input signals are stable

CKE ≤ VIL(max), tCC = 10ns

CKE & CLK ≤ VIL(max), tCC = ∞

CKE ≥ VIH(min), CS ≥ VIH(min), tCC=15ns

Input signals are changed one time during 2clks

All other pins ≥ VDD-0.2V or ≤ 0.2V

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞

input signals are stable

Version

-5 -6 -7

140 120 100

2.5

2

25

18

20

20

35

25

Unit Note

mA 1,2

mA

mA

mA

mA

mA

Operating Current

(Burst Mode)

Refresh Current

Self Refresh Current

IOL = 0 mA

ICC4

Page Burst

2 Banks activated

tCC = tCC(min)

ICC5

tRFC ≥ tRFC(min)

ICC6

CKE ≤ 0.2V

290 270 240 mA 1,2

290 270 240 mA

4

mA

Note: 1. Measured with outputs open.

2. Input signals are changed one time during 2 CLKS.

Elite Semiconductor Memory Technology Inc.

Publication Date: Jun. 2011

Revision: 0.1

4/44

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