M12L128324A-2M Ver la hoja de datos (PDF) - [Elite Semiconductor Memory Technology Inc.

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M12L128324A-2M

1M x 32 Bit x 4 Banks Synchronous DRAM

[Elite Semiconductor Memory Technology Inc. 

ESMT

M12L128324A (2M)

(b) CL =3 ,B L= 4

CLK

i)CMD

DQM

DQ

ii)CMD

DQM

DQ

iii)CMD

DQM

DQ

iv)CMD

DQM

DQ

v)CMD

DQM

DQ

RD WR

D0 D1 D2 D3

RD

WR

D0 D1 D2 D3

RD

WR

D0 D1 D2 D3

RD

WR

Hi-Z

D0 D1 D2 D3

RD

WR

Hi-Z

Q0

D0 D1 D2 D3

*Note1

*Note: 1. To prevent bus contention, there should be at least one gap between data in and data out.

5. Write Interrupted by Precharge & DQM

1)Normal Write (BL=4)

CLK

CMD

WR

DQM

*Note3

PRE

*Note2

DQ

D0 D1 D2 D3

tRDL(min) M a s k e d b y D Q M

*Note:

1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.

2. To inhibit invalid write, DQM should be issued.

3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge interrupt

but only another bank precharge of four banks operation.

Elite Semiconductor Memory Technology Inc.

Publication Date: Mar. 2011

Revision: 1.2

19/44

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