ML9042-XX Ver la hoja de datos (PDF) - LAPIS Semiconductor Co., Ltd.
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ML9042-XX Datasheet PDF : 58 Pages
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LAPIS Semiconductor
FEDL9042-01
ML9042-xx
2) READ MODE (Timing for output to the CPU)
Parameter
RW/SI, RS1, RS0/CSB Setup Time
E/SHTB Pulse Width
RW/SI, RS1, RS0/CSB Hold Time
E/SHTB Rise Time
E/SHTB Fall Time
E/SHTB Pulse Width
E/SHTB Cycle Time
DB0(SO) to DB7 Output Data Delay Time
DB0(SO) to DB7 Output Data Hold Time
Symbol
tB
tW
tA
tr
tf
tL
tC
tD
tO
(VDD = 2.7 to 4.5 V, Ta = –40 to +85C)
Min.
Typ.
Max.
Unit
40
—
—
ns
450
—
—
ns
10
—
—
ns
—
—
125
ns
—
—
125
ns
430
—
—
ns
1000
—
—
ns
—
—
350
ns
20
—
—
ns
Note: A load capacitance of each of DB0(SO) to DB7 must be 50 pF or less.
Parameter
RW/SI, RS1, RS0/CSB Setup Time
E/SHTB Pulse Width
RW/SI, RS1, RS0/CSB Hold Time
E/SHTB Rise Time
E/SHTB Fall Time
E/SHTB Pulse Width
E/SHTB Cycle Time
DB0(SO) to DB7 Output Data Delay Time
DB0(SO) to DB7 Output Data Hold Time
Symbol
tB
tW
tA
tr
tf
tL
tC
tD
tO
(VDD = 4.5 to 5.5 V, Ta = –40 to +85C)
Min.
Typ.
Max.
Unit
40
—
—
ns
220
—
—
ns
10
—
—
ns
—
—
125
ns
—
—
125
ns
220
—
—
ns
500
—
—
ns
—
—
250
ns
20
—
—
ns
Note: A load capacitance of each of DB0(SO) to DB7 must be 50 pF or less.
RS1, RS0/CSB
VIH
VIL
VIH
VIL
RW/SI
E/SHTB
VIH
tB
tr
tL
VIH
VIL
VIL
tD
DB0(SO) to DB7
tC
VIH
tW
tf
tA
VIH
VIL
tO
0.8VDD Output
0.2VDD Data
0.8VDD
0.2VDD
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