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IDT72V3622L10PFG

3.3 VOLT CMOS SyncBiFIFO™ 256 x 36 x 2 512 x 36 x 2 1,024 x 36 x 2

Integrated Device Technology 

IDT72V3622/72V3632/72V3642 CMOS 3.3V SyncBiFIFOTM

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

The Full/Input Ready flag of a FlFO is synchronized to the port clock

that writes data to its array. For both FWFT and IDT Standard modes,

each time a word is written to a FIFO, its write pointer is incremented. The

state machine that controls a Full/Input Ready flag monitors a write

pointer and read pointer comparator that indicates when the FlFO

memory status is full, full-1, or full-2. From the time a word is read from

a FIFO, its previous memory location is ready to be written to in a

minimum of two cycles of the Full/Input Ready flag synchronizing clock.

Therefore, a Full/Input Ready flag is LOW if less than two cycles of the

Full/Input Ready flag synchronizing clock have elapsed since the next

memory write location has been read. The second LOW-to-HIGH

transition on the Full/Input Ready flag synchronizing clock after the read

sets the Full/Input Ready flag HIGH.

A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock

begins the first synchronization cycle of a read if the clock transition occurs at

time tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can

be the first synchronization cycle (see Figures 12 through 15 for FFA/IRA and

FFB/IRB timing diagrams).

ALMOST-EMPTY FLAGS (AEA, AEB)

The Almost-Empty flag of a FIFO is synchronized to the port clock that reads

data from its array. The state machine that controls an Almost-Empty flag monitors

a write pointer and read pointer comparator that indicates when the FIFO

memory status is almost-empty, almost-empty+1, or almost-empty+2. The

almost-empty state is defined by the contents of register X1 for AEB and register

X2 for AEA. These registers are loaded with preset values during a FIFO reset

or programmed from port A (see Almost-Empty flag and Almost-Full flag offset

programming section). An Almost-Empty flag is LOW when its FIFO contains

X or less words and is HIGH when its FIFO contains (X+1) or more words. A

data word present in the FIFO output register has been read from memory.

Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing

clock are required after a FIFO write for its Almost-Empty flag to reflect the new

level of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more

words remains LOW if two cycles of its synchronizing clock have not elapsed

since the write that filled the memory to the (X+1) level. An Almost-Empty flag

is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after

the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition of

an Almost-Empty flag synchronizing clock begins the first synchronization cycle

if it occurs at time tSKEW2 or greater after the write that fills the FIFO to (X+1) words.

Otherwise, the subsequent synchronizing clock cycle may be the first synchro-

nization cycle. (See Figures 16 and 17).

ALMOST-FULL FLAGS (AFA, AFB)

The Almost-Full flag of a FIFO is synchronized to the port clock that writes

data to its array. The state machine that controls an Almost-Full flag monitors a

write pointer and read pointer comparator that indicates when the FIFO

memory status is almost-full, almost-full-1, or almost-full-2. The almost-

COMMERCIAL TEMPERATURE RANGE

full state is defined by the contents of register Y1 for AFA and register Y2

for AFB. These registers are loaded with preset values during a FlFO

reset or programmed from port A (see Almost-Empty flag and Almost-

Full flag offset programming section). An Almost-Full flag is LOW when

the number of words in its FIFO is greater than or equal to (256-Y), (512-

Y), or (1,024-Y) for the IDT72V3622, IDT72V3632, or IDT72V3642

respectively. An Almost-Full flag is HIGH when the number of words in

its FIFO is less than or equal to [256-(Y+1)], [512-(Y+1)], or [1,024-(Y+1)]

for the IDT72V3622, IDT72V3632, or IDT72V3642 respectively. Note that

a data word present in the FIFO output register has been read from

memory.

Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock

are required after a FIFO read for its Almost-Full flag to reflect the new level of

fill. Therefore, the Almost-Full flag of a FIFO containing [256/512/1,024-(Y+1)]

or less words remains LOW if two cycles of its synchronizing clock have not

elapsed since the read that reduced the number of words in memory to [256/

512/1,024-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-to-HIGH

transition of its synchronizing clock after the FIFO read that reduces the number

of words in memory to [256/512/1,024-(Y+1)]. A LOW-to-HIGH transition of an

Almost-Full flag synchronizing clock begins the first synchronization cycle if it

occurs at time tSKEW2 or greater after the read that reduces the number of words

in memory to [256/512/1,024-(Y+1)]. Otherwise, the subsequent synchroniz-

ing clock cycle may be the first synchronization cycle (see Figures 18 and 19).

MAILBOX REGISTERS

Each FIFO has a 36-bit bypass register to pass command and control

information between port A and port B without putting it in queue. The Mailbox

select (MBA, MBB) inputs choose between a mail register and a FIFO for a port

data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data

to the mail1 register when a port A Write is selected by CSA, W/RA, and ENA

and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data

to the mail2 register when a port B Write is selected by CSB, W/RB, and ENB

and with MBB HIGH. Writing data to a mail register sets its corresponding flag

(MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while

the mail flag is LOW.

When data outputs of a port are active, the data on the bus comes from the

FIFO output register when the port Mailbox select input is LOW and from the mail

register when the port mailbox select input is HIGH. The Mail1 Register Flag

(MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port B Read

is selected by CSB, W/RB, and ENB and with MBB HIGH. The Mail2 Register

Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port

A read is selected by CSA, W/RA, and ENA and with MBA HIGH. The data

in a mail register remains intact after it is read and changes only when new data

is written to the register. For mail register and Mail Register Flag timing diagrams,

see Figure 20 and 21.

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