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DS2770

Battery Monitor and Charge Controller

Maxim Integrated 

ELAPSED TIME REGISTER FORMAT Figure 10

DS2770

MSB—Address 02

215 214 213 212 211 210 29 28

MSb

LSb

LSB—Address 03

27 26 25 24 23 22 21 20

MSb

LSb

Units: 0.015625hr

MEMORY

The DS2770 has a 256-byte linear address space with registers for instrumentation, status, and control in

the lower 32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining

address space. All EEPROM and SRAM memory is general purpose except addresses 31h, 32h, 33h, and

34h, which should be written with the default values for the Status Register (31h), Current Offset Register

(32h to 33h), and Charge Time Register (34h). When the MSB of any two-byte register is read, both the

MSB and LSB are latched and held for the duration of the Read Data command to prevent updates during

the read and ensure synchronization between two register bytes. For consistent results, always read the

MSB and the LSB of a two-byte register during the same Read Data command sequence.

EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow

the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from

EEPROM memory actually access shadow RAM. In unlocked EEPROM blocks, the Write Data

command updates shadow RAM. In locked EEPROM blocks, the Write Data command is ignored. The

Copy Data command copies the contents of shadow RAM to EEPROM in an unlocked block of

EEPROM, but has no effect on locked blocks. The Recall Data command copies the contents of a block

of EEPROM to shadow RAM.

Lockable EEPROM is byte programmable and functions as EEPROM until reprogramming is disabled by

the user. The lockable EEPROM can be locked in separate blocks and operate as general EEPROM until

locked by the Lock command [6Axxh]. Reprogramming of the lockable EEPROM blocks is permanently

disabled once the Lock command is used. Addresses 20 to 2Fh comprise a first 16-byte block, addresses

30 to 3Fh comprise a second 16-byte block, and addresses 40 to 47h comprise a third 8-byte block.

Within the second block, address 31h holds the Status Register initialization data, addresses 32h and 33h

hold the Current Offset Register, and address 34h holds the Charge Time Register initialization data. The

Status Register initialization data is supplied to the Status Register in location address 01h on either a

device power up or upon the execution of the Refresh command [63h]. The charge time initialization data

is supplied to the Charge Time Register in address 06h upon the start of fast charge. The Status Register

and the Charge Time Register are both initialized directly from the EEPROM and not from the shadow

RAM. However, the current offset data is supplied directly from the shadow RAM. See the sections on

the Status Register and the Charge Time Register for more detailed information. See the detailed Memory

Map in Figure 11 for more information on the DS2770 memory.

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