LP62S16128B-T Ver la hoja de datos (PDF) - AMIC Technology

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LP62S16128B-T

128K X 16 BIT LOW VOLTAGE CMOS SRAM

AMIC Technology 

AC Test Conditions

Input Pulse Levels

Input Rise And Fall Time

Input and Output Timing Reference Levels

Output Load

LP62S16128B-T Series

0.4V to 2.4V

5 ns

1.5V

See Figures 1 and 2

TTL

TTL

CL

30pF

CL

5pF

* Including scope and jig.

* Including scope and jig.

Figure 1. Output Load

Data Retention Characteristics (TA = -25°C to 85°C)

Figure 2. Output Load for tCLZ, tOLZ, tBHZ, tBLZ,

tCHZ, tOHZ, tWHZ, and tOW

Symbol

Parameter

VDR

VCC for Data Retention

Min. Max.

2.0

3.6

ICCDR

Data Retention Current

-

3*

tCDR

Chip Disable to Data Retention Time

0

-

tR

Operation Recovery Time

tRC

-

tVR

VCC Rising Time from Data Retention

Voltage to Operating Voltage

5

-

* LP62S16128B-70LLT

ICCDR: max. 1µA at TA = 0°C to + 40°C

Unit

Conditions

CE ≥ VCC - 0.2V or

V

LB = HB ≥ VCC-0.2V

VCC = 2V,

CE ≥ VCC - 0.2V or

µA

LB = HB ≥ VCC-0.2V

VIN ≥ VCC - 0.2V or VIN ≤ 0.2V

ns

ns See Retention Waveform

ms

(June, 2004, Version 1.3)

11

AMIC Technology, Corp.

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