ISL6532B Ver la hoja de datos (PDF) - Renesas Electronics
Número de pieza
componentes Descripción
Lista de partido
ISL6532B Datasheet PDF : 15 Pages
| |||
ISL6532B
VOSC
OSC
PWM
COMPARATOR
-
+
DRIVER
DRIVER
VIN
LO
PHASE CO
VDDQ
ZFB
VE/A
-
+
ZIN
ERROR REFERENCE
AMP
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C1
C2
R2
ZFB
VDDQ
ZIN
C3 R3
R1
COMP
-
FB
+
R4
ISL6532B
REFERENCE
VDDQ
=
0.8
1
+
RR-----14-
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
1. Pick Gain (R2/R1) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error Amplifier’s Open-Loop Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
FZ1 = -2---------x-----R--1--2-----x------C----2-
FZ2 = 2----------x-------R-----1----+-1----R-----3-------x------C----3-
FP1
=
---------------------------1-----------------------------
2
x
R2
x
C-C----11-----+x-----CC----2-2-
FP2 = -2---------x-----R--1--3-----x------C----3-
Figure 6 shows an asymptotic plot of the DC-DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not
shown in Figure 6. Using the above guidelines should give a
Compensation Gain similar to the curve plotted. The open loop
error amplifier gain bounds the compensation gain. Check the
compensation gain at FP2 with the capabilities of the error
amplifier. The Closed Loop Gain is constructed on the graph of
Figure 6 by adding the Modulator Gain (in dB) to the
Compensation Gain (in dB). This is equivalent to multiplying
the modulator transfer function to the compensation transfer
function and plotting the gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45
degrees. Include worst case component variations when
determining phase margin.
100
FZ1 FZ2 FP1 FP2
80
OPEN LOOP
60
ERROR AMP GAIN
40
20LOG
20 (R2/R1)
20LOG
0
(VIN/VOSC)
MODULATOR
-20
GAIN
-40
FLC
FESR
-60
10
100
1K 10K 100K
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Output Voltage Selection
The output voltage of the VDDQ PWM converter can be
programmed to any level between VIN and the internal
reference, 0.8V. An external resistor divider is used to scale
the output voltage relative to the reference voltage and feed it
back to the inverting input of the error amplifier, see Figure 6.
However, since the value of R1 affects the values of the rest of
the compensation components, it is advisable to keep its value
less than 5k. Depending on the value chosen for R1, R4 can
be calculated based on the following equation:
R4 = V-----RD----D1----Q------–0---.-0-8---.-V8----V--
If the output voltage desired is 0.8V, simply route VDDQ back
to the FB pin through R1, but do not populate R4.
The output voltage for the internal VTT linear regulator is set
internal to the ISL6532B to track the VDDQ voltage by 50%.
There is no need for external programming resistors.
Component Selection Guidelines
Output Capacitor Selection - PWM Buck Converter
An output capacitor is required to filter the inductor current and
supply the load transient current. The filtering requirements are
FN9120 Rev 3.00
Jul 2004
Page 11 of 15
Share Link: 