ISL8013 Ver la hoja de datos (PDF) - Renesas Electronics
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ISL8013 Datasheet PDF : 18 Pages
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ISL8013
Theory of Operation
The ISL8013 is a step-down switching regulator
optimized for battery-powered handheld applications.
The regulator operates at 1MHz fixed switching
frequency under heavy load conditions to allow smaller
external inductors and capacitors to be used for minimal
printed-circuit board (PCB) area. At light load, the
regulator reduces the switching frequency, unless forced
to the fixed frequency, to minimize the switching loss and
to maximize the battery life. The quiescent current when
the output is not loaded is typically only 35µA. The
supply current is typically only 0.1µA when the regulator
is shut down.
PWM Control Scheme
Pulling the SYNCH pin HI (>2.5V) forces the converter
into PWM mode, regardless of output current. The
ISL8013 employs the current-mode pulse-width
modulation (PWM) control scheme for fast transient
response and pulse-by-pulse current limiting. Figure 2
shows the block diagram. The current loop consists of the
oscillator, the PWM comparator, current sensing circuit
and the slope compensation for the current loop stability.
The gain for the current sensing circuit is typically
250mV/A. The control reference for the current loops
comes from the error amplifier's (EAMP) output.
The PWM operation is initialized by the clock from the
oscillator. The P-Channel MOSFET is turned on at the
beginning of a PWM cycle and the current in the
MOSFET starts to ramp up. When the sum of the current
amplifier CSA and the slope compensation (237mV/µs)
reaches the control reference of the current loop, the
PWM comparator COMP sends a signal to the PWM logic
to turn off the P-MOSFET and turn on the N-Channel
MOSFET. The N-MOSFET stays on until the end of the
PWM cycle. Figure 36 shows the typical operating
waveforms during the PWM operation. The dotted lines
illustrate the sum of the slope compensation ramp and
the current-sense amplifier’s CSA output.
The output voltage is regulated by controlling the VEAMP
voltage to the current loop. The bandgap circuit outputs
a 0.8V reference voltage to the voltage loop. The
feedback signal comes from the VFB pin. The soft-start
block, only affects the operation during the start-up and
will be discussed separately. The error amplifier is a
transconductance amplifier that converts the voltage
error signal to a current output. The voltage loop is
internally compensated with the 27pF and 390k RC
network. The maximum EAMP voltage output is precisely
clamped to 1.6V.
VEAMP
VCSA
DUTY
CYCLE
IL
VOUT
FIGURE 36. PWM OPERATION WAVEFORMS
SKIP Mode
Pulling the SYNCH pin LO (<0.4V) forces the converter
into PFM mode. The ISL8013 enters a pulse-skipping
mode at light load to minimize the switching loss by
reducing the switching frequency. Figure 37 illustrates
the skip-mode operation. A zero-cross sensing circuit
shown in Figure 2 monitors the N-MOSFET current for
zero crossing. When 8 consecutive cycles of the inductor
current crossing zero are detected, the regulator enters
the skip mode. During the eight detecting cycles, the
current in the inductor is allowed to become negative.
The counter is reset to zero when the current in any cycle
does not cross zero.
Once the skip mode is entered, the pulse modulation
starts being controlled by the SKIP comparator shown in
Figure 2. Each pulse cycle is still synchronized by the
PWM clock. The P-MOSFET is turned on at the clock's
rising edge and turned off when the output is higher than
1.5% of the nominal regulation or when its current
reaches the peak Skip current limit value. Then the
inductor current is discharging to 0A and stays at zero.
The internal clock is disabled.The output voltage reduces
gradually due to the load current discharging the output
capacitor. When the output voltage drops to the nominal
voltage, the P-MOSFET will be turned on again at the
rising edge of the internal clock as it repeats the previous
operations.
The regulator resumes normal PWM mode operation
when the output voltage drops 1.5% below the nominal
voltage.
Synchronization Control
The frequency of operation can be synchronized up to
4MHz by an external signal applied to the SYNCH pin.
The falling edge on the SYNCH triggers the rising edge of
the LX pulse. Make sure that the minimum on time of the
LX node is greater than 140ns.
Overcurrent Protection
The overcurrent protection is realized by monitoring the
CSA output with the OCP comparator, as shown in
Figure 2. The current sensing circuit has a gain of
FN6309 Rev 3.00
November 23, 2009
Page 13 of 18
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