ISL8540 Ver la hoja de datos (PDF) - Renesas Electronics
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ISL8540 Datasheet PDF : 17 Pages
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ISL8540
VOSC
OSC
PWM
COMPARATOR
+-
DRIVER
DRIVER
ZFB
VE/A
+-
ZIN
ERROR REFERENCE
AMP
VIN
LO
LX
VOUT
D
CO
ESR
(PARASITIC)
DETAILED COMPENSATION COMPONENTS
C10
C6
R4
ZFB
VOUT
ZIN
C7 R6
COMP
R2
gm+-
FB
R3
ISL8540
REFERENCE
VOUT
=
1.2
0
1
+
R-R----23-
FIGURE 28. VOLTAGE-MODE BUCK CONVERTER
COMPENSATION DESIGN AND OUTPUT
VOLTAGE SELECTION
modulator is simply the input voltage (VIN) divided by the peak-
to-peak oscillator voltage VOSC. The ISL8540 incorporates a
feed forward loop that accounts for changes in the input voltage.
This maintains a constant modulator gain.
Modulator Break Frequency Equations
fLC=
---------------------1---------------------
2 x LO x CO
fESR= 2----------x-----E----S--1---R------x-----C-----O---
(EQ. 11)
The compensation network consists of the transconductance
amplifier (internal to the ISL8540) and the impedance networks
ZIN and ZFB. The goal of the compensation network is to
provide a closed loop transfer function with the highest 0dB
crossing frequency (f0dB) and adequate phase margin. Phase
margin is the difference between the closed loop phase at f0dB
and 180°. The equations in the following section relate the
compensation network’s poles, zeros and gain to the
components (R2, R3, R4, R6, C10, C6, and C7) in Figure 28.
Use these guidelines for locating the poles and zeros of the
compensation network:
1. Pick Gain (R3gm/(R2+R3) for desired converter bandwidth.
2. Place 1ST Zero Below Filter’s Double Pole (~75% fLC).
3. Place 2ND Zero at Filter’s Double Pole.
4. Place 1ST Pole at the ESR Zero.
5. Place 2ND Pole at Half the Switching Frequency.
6. Check Gain against Error transconductance’s Open-Loop
Gain.
7. Estimate Phase Margin - Repeat if Necessary.
Compensation Break Frequency Equations
fZ1 = 2------------------R--------4--------------g--g--1--m--m------------+----------1--------------C-----6-
fP1 = -2-------R----1-6-------C-----7-
(EQ. 12)
fZ2 = -2-------R----1-2-------C-----7-
fP2 = 2--------R-----4-1------C-----1---0-
Assumption: R6<<R2, R6<<R3, and C10<<C6.
Figure 29 shows an asymptotic plot of the DC/DC converter’s
gain vs frequency. The actual Modulator Gain has a high gain
peak due to the high Q factor of the output filter and is not shown
in Figure 29. Using the guidelines in “Modulator Break
Frequency Equations” on page 14 should give a Compensation
Gain similar to the curve plotted. The open loop error amplifier
gain bounds the compensation gain. Check the compensation
gain at FP2 with the capabilities of the error amplifier. The
Closed Loop Gain is constructed on the graph of Figure 29 by
adding the Modulator Gain (in dB) to the Compensation Gain (in
dB). This is equivalent to multiplying the modulator transfer
function to the compensation transfer function and plotting the
gain.
The compensation gain uses external impedance networks
ZFB and ZIN to provide a stable, high bandwidth (BW) overall
loop. A stable control loop has a gain crossing with
-20dB/decade slope and a phase margin greater than 45°.
Include worst case component variations when determining
phase margin.
100
FZ1 FZ2 FP1 FP2
80
60
OPEN LOOP
ERROR AMP GAIN
40
20LOG
20 (R4/R2)
20LOG
0
(VIN/VOSC)
MODULATOR
-20
GAIN
-40
-60
FLC
FESR
10
100
1k
10k 100k
COMPENSATION
GAIN
CLOSED LOOP
GAIN
1M 10M
FREQUENCY (Hz)
FIGURE 29. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
A more detailed explanation of voltage mode control of a buck
regulator can be found in Tech Brief TB417, titled “Designing
Stable Compensation Networks for Single Phase Voltage
Mode Buck Regulators.”
FN6495 Rev 5.00
September 9, 2008
Page 14 of 17
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