ISL90842UIV1427Z-TK Ver la hoja de datos (PDF) - Renesas Electronics

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ISL90842UIV1427Z-TK

Quad Digitally Controlled Variable Resistors Low Noise, Low Power I2C Bus, 256 Taps

Renesas Electronics 

ISL90842

The ISL90842 responds with an ACK after recognition of a

START condition followed by a valid Identification Byte, and

once again after successful receipt of an Address Byte. The

ISL90842 also responds with an ACK after receiving a Data

Byte of a write operation. The master must respond with an

ACK after receiving a Data Byte of a read operation

A valid Identification Byte contains 01010 as the five MSBs,

and the following two bits matching the logic values present

at pins A1 and A0. The LSB is the Read/Write bit. Its value is

SCL

“1” for a Read operation, and “0” for a Write operation (See

Table 1).

TABLE 1. IDENTIFICATION BYTE FORMAT

Logic values at pins A1, and A0 respectively

0

1

0

1

0

A1

A0 R/W

(MSB)

(LSB)

SDA

START

DATA

DATA

DATA

STABLE CHANGE STABLE

STOP

FIGURE 9. VALID DATA CHANGES, START, AND STOP CONDITIONS

SCL FROM

MASTER

1

SDA OUTPUT FROM

TRANSMITTER

8

9

HIGH IMPEDANCE

SDA OUTPUT FROM

RECEIVER

HIGH IMPEDANCE

START

ACK

FIGURE 10. ACKNOWLEDGE RESPONSE FROM RECEIVER

SIGNALS FROM

THE MASTER

WRITE

S

T

A

R

T

IDENTIFICATION

BYTE

ADDRESS

BYTE

S

DATA

T

BYTE

O

P

SIGNAL AT SDA

0 1 0 1 0 A1 A0 0 0 0 0 0 0 0

SIGNALS FROM

THE ISL90842

A

A

A

C

C

C

K

K

K

FIGURE 11. BYTE WRITE SEQUENCE

FN8096 Rev 1.00

January 16, 2006

Page 8 of 10

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