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AD9510-VCO/PCBZ

1.2 GHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Eight Outputs

Analog Devices

AD9510-VCO/PCBZ Datasheet PDF : 56 Pages

1 2 3 4 5 6 7 8 9 10 Next Last

Data Sheet

Parameter

CLK1-TO-LVDS ADDITIVE PHASE NOISE

CLK1 = 622.08 MHz, OUT= 622.08 MHz

Divide Ratio = 1

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

CLK1 = 622.08 MHz, OUT = 155.52 MHz

Divide Ratio = 4

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

CLK1 = 491.52 MHz, OUT = 245.76 MHz

Divide Ratio = 2

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

CLK1 = 491.52 MHz, OUT = 122.88 MHz

Divide Ratio = 4

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

CLK1 = 245.76 MHz, OUT = 245.76 MHz

Divide Ratio = 1

At 10 Hz Offset

At 100 Hz Offset

At 1 kHz Offset

At 10 kHz Offset

At 100 kHz Offset

At 1 MHz Offset

>10 MHz Offset

Min Typ Max Unit

AD9510

Test Conditions/Comments

Distribution Section only; does not include

PLL or external VCO/VCXO

−100

−110

−118

−129

−135

−140

−148

dBc/Hz

−112

−122

−132

−142

−148

−152

−155

dBc/Hz

−108

−118

−128

−138

−145

−148

−154

dBc/Hz

−118

−129

−136

−147

−153

−156

−158

dBc/Hz

−108

−118

−128

−138

−145

−148

−155

dBc/Hz

Rev. B | Page 9 of 56

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