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EV-ADF4196SD1Z

Low Phase Noise, Fast Settling, 6 GHz PLL Frequency Synthesizer

Analog Devices 

Data Sheet

APPLICATIONS INFORMATION

LOCAL OSCILLATOR FOR A GSM BASE STATION

Figure 37 shows the ADF4196 being used with a VCO to

produce the LO for a GSM1800 base station. For GSM, the

REFIN signal can be any integer multiple of 13 MHz, but the

main requirement is that the slew rate be at least 300 V/µs.

The 104 MHz, 5 dBm input sine wave shown in Figure 37

satisfies this requirement.

Recommended parameters for the various GSM/DCS/PCS

synthesizers are listed in Table 10.

Table 10. Recommended Setup Parameters

GSM900

DCS1800/PCS1900

Parameter

Tx

Rx

Tx

Rx

Loop BW

60 kHz 40 kHz

60 kHz 40 kHz

PFD

13 MHz 26 MHz 13 MHz 13 MHz

MOD

65

130

65

65

Dither

Off

Off

Off

Off

Prescaler

4/5

4/5

8/9

8/9

ICP Timer

28

78

SW1, SW2,

35

85

SW3 Timers

28

38

35

45

VCO KV

18 MHz/V 18 MHz/V 38 MHz/V 38 MHz/V

Loop Bandwidth and PFD Frequency

A 60 kHz loop bandwidth is narrow enough to attenuate the

PLL phase noise and spurs to the required level for a Tx low.

A 40 kHz bandwidth is necessary to meet the GSM900 Rx

synthesizer’s particularly tough phase noise and spur requirements

at ±800 kHz offsets. To get the lowest spur levels at ±800 kHz

offsets for Rx, the Σ-Δ modulator should be run at the highest over-

sampling rate possible. Therefore, for GSM900 Rx, a 26 MHz PFD

frequency is chosen, and MOD = 130 is required for 200 kHz steps.

Because this value of MOD is divisible by two, certain FRAC

channels have a 100 kHz fractional spur. This is attenuated by the

40 kHz loop filter and, therefore, is not a concern. However, the

60 kHz loop filter that is recommended for Tx has a closed-loop

response that peaks close to 100 kHz. Therefore, a 13 MHz PFD

with MOD = 65, which avoids the 100 kHz spur, is the best choice

for a Tx synthesizer.

Dither

Dither off should be selected for the lowest rms phase error.

Prescaler

The 8/9 prescaler should be selected for the DCS and PCS bands.

The 4/5 prescaler allows an N divider range low enough to cover

the GSM900 Tx and Rx bands with either a 13 MHz or 26 MHz

PFD frequency.

ADF4196

Timer Values for Tx

To comply with the GSM spectrum due to switching requirements,

the Tx synthesizer should not switch frequency until the PA output

power has ramped down by at least 50 dB. If it takes 10 µs to ramp

down to this level, only the last 20 µs of the 30 µs guard period is

available for the Tx synthesizer to lock to final frequency and phase.

In fast lock mode, the Tx loop bandwidth is widened by a factor

of 8 to 480 kHz and, therefore, the PLL achieves frequency lock

for a jump across the entire band in <6 µs. After this, the PA

power can start to ramp up again, and the loop bandwidth can

be restored to the final value. With the ICP timer = 28, the charge

pump current reduction begins at ~8.6 µs. When the SW1, SW2,

and SW3 timers = 35, the current reaches its final value before

the loop filter switches open at ~10.8 µs.

With these timer values, the phase disturbance created when

the bandwidth is reduced settles back to its final value by 20 µs,

in time for the start of the active part of the GSM burst. If faster

phase settling is desired with the 60 kHz bandwidth setting, the

timer values can be reduced further but should not be brought

less than the 6 µs that is required to achieve frequency lock in

wide bandwidth mode.

Timer Values for Rx

The 40 kHz Rx loop bandwidth is increased by a factor of 8 to

approximately 320 kHz during fast lock. With the Rx timer values

shown in Table 10, the bandwidth is reduced after ~12 µs, which

allows sufficient time for the phase disturbance to settle back

before the start of the active part of the Rx time slot at 30 µs.

As in the Tx synthesizer case, faster Rx settling can be achieved by

reducing these timer values, their lower limit being determined

by the time it takes to achieve frequency lock in wide bandwidth

mode. In addition, the DCS and PCS Rx synthesizers have relaxed

800 kHz blocker specifications and, thus, can tolerate a wider

loop bandwidth, which allows correspondingly faster settling.

VCO KV

In general, the VCO gain, KV, should be set as low as possible to

minimize the reference and integer boundary spur levels that arise

due to feedthrough mechanisms. When deciding on the optimum

VCO KV, a good choice is to allow 2 V to tune across the desired

band, centered on the available tuning range. With VP3 regulated

to 5.5 V ± 100 mV, the tuning range available is 2.8 V.

Loop Filter Components

For good settling performance, it is important that capacitors

with low dielectric absorption be used in the loop filter. Ceramic

NPO C0G capacitors are a good choice for this application.

A 2% tolerance is recommended for loop filter capacitors and

1% for resistors. A 10% tolerance is adequate for the inductor, L1.

Rev. D | Page 25 of 28

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