ADM1073ARUZ-REEL7 Ver la hoja de datos (PDF) - Analog Devices
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ADM1073ARUZ-REEL7 Datasheet PDF : 24 Pages
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Data Sheet
ADM1073
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
RESTART 1
14 SHDN
VIN 2
13 TIMER
PWRGD 3 ADM1073 12 UV
SS 4 TOP VIEW 11 OV
SENSE 5 (Not to Scale) 10 DRAIN
VEE 6
LATCHED 7
9 GATE
8 SPLYGD
Figure 2. Pin Configuration
Table 3. Pin Function Descriptions
Pin Number Mnemonic
Function
1
RESTART
Input Pin. Edge-triggered 5-second shutdown and automatic restart.
2
VIN
Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via shunt resistor. A 1 µF
capacitor to VEE is recommended on the VIN pin.
3
PWRGD
Open Drain Output. Signals that the hot swap is complete.
4
SS
Analog Pin for Soft Start. An external capacitor on this pin sets the ramp rate of the inrush current
profile. This pin can be overdriven to alter the current limit control loop threshold.
5
SENSE
Voltage Input from External Sense Resistor.
6
VEE
Ground Supply to Chip (usually a −48 V system supply). Also low-side sense resistor connection.
7
LATCHED
Open Drain Output. Signals the end of the PWM retry period after a current fault.
8
SPLYGD
Open Drain Output. Signals that the device is not in reset and that the supply is in operating voltage
window.
9
GATE
Output to External FET Gate Drive.
10
DRAIN
Analog Input for Monitoring of FET Drain Voltage.
11
OV
Input Pin for Overvoltage Detection Circuitry.
12
UV
Input Pin for Undervoltage Detection Circuitry.
13
TIMER
Analog Pin. An external capacitor on this pin sets the maximum allowable time in current limit, the
PWM on-time, and the PWM duty cycle.
14
SHDN
Input Pin. Level-triggered device shutdown and reset.
Rev. B | Page 7 of 24
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