CY23S08SXI-4T(2007) Ver la hoja de datos (PDF) - Cypress Semiconductor

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CY23S08SXI-4T
(Rev.:2007)

3.3V Zero Delay Buffer

Cypress Semiconductor 

CY23S08

Switching Characteristics for CY23S08SC-XX Commercial Temperature Devices (continued)

Parameter[8]

Name

Test Conditions

t3

Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF

load

t3

Rise Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF

load

t3

Rise Time[7] (–1H, -2H) Measured between 0.8V and 2.0V, 30-pF

load

t4

Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 30-pF

load

t4

Fall Time[7] (–1, –2, –3, –4) Measured between 0.8V and 2.0V, 15-pF

load

t4

Fall Time[7] (–1H, 2H)

Measured between 0.8V and 2.0V, 30-pF

load

Min Typ. Max Unit

—

—

2.20

ns

—

—

1.50

ns

—

—

1.50

ns

—

—

2.20

ns

—

—

1.50

ns

—

—

1.25

ns

t5

Output to Output Skew on All outputs equally loaded

same Bank (–1)[7]

45

200

ps

Output to Output Skew on All outputs equally loaded

same Bank

(–1H,–2,–2H,–3)[7]

—

105

150

ps

Output to Output Skew on All outputs equally loaded

same Bank (–4)[7]

—

70

100

ps

Output to Output Skew

(–1H, -2H)

All outputs equally loaded

—

—

200

ps

Output Bank A to Output All outputs equally loaded

Bank B Skew (–1,–2, –3)

—

—

300

ps

Output Bank A to Output All outputs equally loaded

Bank B Skew (–4)

—

—

215

ps

Output Bank A to Output All outputs equally loaded

Bank B Skew (–1H)

—

—

250

ps

t6

t7

t8

tJ

tJ

tLOCK

Delay, REF Rising Edge to

FBK Rising Edge[7]

Measured at VDD/2

–250

—

+275 ps

Device to Device Skew[7] Measured at VDD/2 on the FBK pins of

devices

—

—

700

ps

Output Slew Rate[7]

Measured between 0.8V and 2.0V on –1H,

1

—

–2H device using Test Circuit #2

V/ns

Cycle to Cycle Jitter[7]

(–1, –1H)

Measured at 66.67 MHz, loaded outputs, 15, —

30-pF loads: 133 MHz, 15-pF load

65

125

ps

Cycle to Cycle Jitter[7]

Measured at 66.67 MHz, loaded outputs,

—

85

300

ps

(–2)

15-pF load

Cycle to Cycle Jitter[7]

Measured at 66.67 MHz, loaded outputs,

—

—

400

ps

(–2)

30-pF load

Cycle to Cycle Jitter[7]

(–3,–4)

Measured at 66.67 MHz, loaded outputs

15, 30-pF loads

—

—

200

ps

PLL Lock Time[7]

Stable power supply, valid clocks presented —

—

1.0

ms

on REF and FBK pins

Document #: 38-07265 Rev. *G

Page 5 of 10

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