CY8CMBR2110-24LQXI Ver la hoja de datos (PDF) - Cypress Semiconductor
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CY8CMBR2110-24LQXI Datasheet PDF : 71 Pages
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Typical Circuits
Schematic 1: Ten Buttons with Ten GPOs
Figure 1. CY8CMBR2110 Schematic 1
CY8CMBR2110
In Figure 1, the device is configured in the following manner:
■ CS0–CS9 pins: 560 to CapSense buttons
❐ Ten CapSense buttons (CS0–CS9)
■ GPO0–GPO9 pins: LED and 5 kto VDD
❐ CapSense buttons driving 10 LEDs (GPO0-GPO9)
■ CMOD pin: 2.2 nF to ground
❐ Modulating capacitor
■ XRES pin: Floating
❐ For external reset
■ BuzzerOut0 pin: To buzzer
❐ AC buzzer (1-pin)
❐ Buzzer second pin to Ground
■ BuzzerOut1 pin: LED and 5 k to Ground
❐ Used as Host Controlled GPO
■ HostControlGPO0, HostControlGPO1: LED and 5 k to
Ground
❐ Two Host Controlled GPOs
■ HostControlGPO0, HostControlGPO1: Floating
❐ Host Controlled GPOs disabled
■ I2C_SDA, I2C_SCL pins: 330 to I2C header
❐ For I2C communication
■ Attention/Sleep pin: To host
❐ For controlling I2C communication, power consumption, and
device operating mode
Document Number: 001-74494 Rev. *B
Page 4 of 71
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